| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250623102940.214269-1-laura.nao@collabora.com>
Date: Mon, 23 Jun 2025 12:29:10 +0200
From: Laura Nao <laura.nao@...labora.com>
To: mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com,
p.zabel@...gutronix.de,
richardcochran@...il.com
Cc: guangjie.song@...iatek.com,
wenst@...omium.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
netdev@...r.kernel.org,
kernel@...labora.com,
Laura Nao <laura.nao@...labora.com>
Subject: [PATCH 00/30] Add support for MT8196 clock controllers
This patch series introduces support for the clock controllers on the
MediaTek MT8196 platform, following up on an earlier submission[1].
MT8196 uses a hardware voting mechanism to control some of the clock muxes
and gates, along with a fence register responsible for tracking PLL and mux
gate readiness. The series introduces support for these voting and fence
mechanisms, and includes drivers for all clock controllers on the platform.
[1] https://lore.kernel.org/all/20250307032942.10447-1-guangjie.song@mediatek.com/
AngeloGioacchino Del Regno (2):
dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding
clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers
Laura Nao (28):
clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control
clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC
clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and
FENC
clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()
clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC
clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use
mtk_gate struct
clk: mediatek: clk-gate: Add ops for gates with HW voter
clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
dt-bindings: clock: mediatek: Describe MT8196 peripheral clock
controllers
clk: mediatek: Add MT8196 apmixedsys clock support
clk: mediatek: Add MT8196 topckgen clock support
clk: mediatek: Add MT8196 topckgen2 clock support
clk: mediatek: Add MT8196 vlpckgen clock support
clk: mediatek: Add MT8196 peripheral clock support
clk: mediatek: Add MT8196 ufssys clock support
clk: mediatek: Add MT8196 pextpsys clock support
clk: mediatek: Add MT8196 adsp clock support
clk: mediatek: Add MT8196 I2C clock support
clk: mediatek: Add MT8196 mcu clock support
clk: mediatek: Add MT8196 mdpsys clock support
clk: mediatek: Add MT8196 mfg clock support
clk: mediatek: Add MT8196 disp0 clock support
clk: mediatek: Add MT8196 disp1 clock support
clk: mediatek: Add MT8196 disp-ao clock support
clk: mediatek: Add MT8196 ovl0 clock support
clk: mediatek: Add MT8196 ovl1 clock support
clk: mediatek: Add MT8196 vdecsys clock support
clk: mediatek: Add MT8196 vencsys clock support
.../bindings/clock/mediatek,mt8196-clock.yaml | 79 ++
.../clock/mediatek,mt8196-sys-clock.yaml | 76 +
drivers/clk/mediatek/Kconfig | 78 +
drivers/clk/mediatek/Makefile | 14 +
drivers/clk/mediatek/clk-gate.c | 106 +-
drivers/clk/mediatek/clk-gate.h | 3 +
drivers/clk/mediatek/clk-mt8196-adsp.c | 193 +++
drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 203 +++
drivers/clk/mediatek/clk-mt8196-disp0.c | 169 +++
drivers/clk/mediatek/clk-mt8196-disp1.c | 170 +++
.../clk/mediatek/clk-mt8196-imp_iic_wrap.c | 117 ++
drivers/clk/mediatek/clk-mt8196-mcu.c | 166 +++
drivers/clk/mediatek/clk-mt8196-mdpsys.c | 187 +++
drivers/clk/mediatek/clk-mt8196-mfg.c | 150 ++
drivers/clk/mediatek/clk-mt8196-ovl0.c | 154 ++
drivers/clk/mediatek/clk-mt8196-ovl1.c | 153 ++
drivers/clk/mediatek/clk-mt8196-peri_ao.c | 144 ++
drivers/clk/mediatek/clk-mt8196-pextp.c | 131 ++
drivers/clk/mediatek/clk-mt8196-topckgen.c | 1257 +++++++++++++++++
drivers/clk/mediatek/clk-mt8196-topckgen2.c | 662 +++++++++
drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 109 ++
drivers/clk/mediatek/clk-mt8196-vdec.c | 253 ++++
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c | 78 +
drivers/clk/mediatek/clk-mt8196-venc.c | 235 +++
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 769 ++++++++++
drivers/clk/mediatek/clk-mtk.c | 16 +
drivers/clk/mediatek/clk-mtk.h | 23 +
drivers/clk/mediatek/clk-mux.c | 119 +-
drivers/clk/mediatek/clk-mux.h | 76 +
drivers/clk/mediatek/clk-pll.c | 46 +-
drivers/clk/mediatek/clk-pll.h | 9 +
.../dt-bindings/clock/mediatek,mt8196-clock.h | 867 ++++++++++++
.../reset/mediatek,mt8196-resets.h | 26 +
33 files changed, 6814 insertions(+), 24 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
create mode 100644 drivers/clk/mediatek/clk-mt8196-adsp.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c
create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h
create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h
--
2.39.5
Powered by blists - more mailing lists