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Message-ID: <20250623120058.109036-1-angelogioacchino.delregno@collabora.com>
Date: Mon, 23 Jun 2025 14:00:55 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: jianjun.wang@...iatek.com
Cc: ryder.lee@...iatek.com,
bhelgaas@...gle.com,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
manivannan.sadhasivam@...aro.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com,
linux-pci@...r.kernel.org,
linux-mediatek@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
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Subject: [PATCH v1 0/3] mediatek-gen3: Add support for MT8196/MT6991
This series adds (at least partial) support for the MediaTek MT8196
Chromebook SoC and for the MT6991 Dimensity 9400 Smartphone SoC's
PCI-Express controller.
Some strange PEXTP settings were omitted, as the intention is to find
a way to set those bits *outside* of the PCI-Express driver itself as
the downstream implementation is using ugly syscons to make the PCIe
controller driver to change bits inside of a clock controller.
In the meanwhile, this is a set of clean changes that are required for
the controller inside those SoCs in *any* case; further development
will occur, with high hopes to find a solution outside of this driver.
AngeloGioacchino Del Regno (3):
PCI: mediatek-gen3: Implement sys clock ready time setting
dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC
.../bindings/pci/mediatek-pcie-gen3.yaml | 35 +++++++++++++++++++
drivers/pci/controller/pcie-mediatek-gen3.c | 24 +++++++++++++
2 files changed, 59 insertions(+)
--
2.49.0
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