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Message-ID: <20250624153318.GA1477975@bhelgaas>
Date: Tue, 24 Jun 2025 10:33:18 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kwilczynski@...nel.org" <kwilczynski@...nel.org>,
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	"linus.walleij@...aro.org" <linus.walleij@...aro.org>,
	"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
	"linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
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	"yuxiaozhang@...gle.com" <yuxiaozhang@...gle.com>,
	BMC-SW <BMC-SW@...eedtech.com>
Subject: Re: 回覆: [PATCH 7/7] pci: aspeed:
 Add ASPEED PCIe host controller driver

On Fri, Jun 20, 2025 at 06:05:20AM +0000, Jacky Chou wrote:
> > > Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC
> > > initialization, reset, clock, IRQ domain, and MSI domain setup.
> > > Implement platform-specific setup and register configuration for
> > > ASPEED. And provide PCI config space read/write and INTx/MSI interrupt
> > > handling.

> > > +static int aspeed_ast2600_rd_conf(struct pci_bus *bus, unsigned int devfn,
> > > +				  int where, int size, u32 *val)
> > > +{
> > > +	struct aspeed_pcie *pcie = bus->sysdata;
> > > +	u32 bdf_offset;
> > > +	int rx_done_fail = 0, slot = PCI_SLOT(devfn);
> > > +	u32 cfg_val, isr, type = 0;
> > > +	u32 link_sts = 0;
> > > +	int ret;
> > > +
> > > +	/* Driver may set unlock RX buffere before triggering next TX config
> > > +*/
> > > +	writel(PCIE_UNLOCK_RX_BUFF | readl(pcie->reg + H2X_DEV_CTRL),
> > > +	       pcie->reg + H2X_DEV_CTRL);
> > > +
> > > +	if (bus->number == 128 && slot != 0 && slot != 8)
> > > +		return PCIBIOS_DEVICE_NOT_FOUND;
> > > +	type = (bus->number > 128);
> > 
> > Weird.  What's all this?  Some kind of device you want to hide?
> > Deserves a hint about what's special.
> 
> The bus range in our AST2600 design is just starting from 128.
> There is no something special.  I will use the child_ops that is in
> struct pci_host_bridge to distinguish the rc bridge and the other
> bus.

Is the 128 root bus number hardwired into the RC?  Maybe it should be
described in DT?

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