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Message-ID: <aFr2VREWciBYuWGt@lizhi-Precision-Tower-5810>
Date: Tue, 24 Jun 2025 15:02:45 -0400
From: Frank Li <Frank.li@....com>
To: Laurentiu Mihalcea <laurentiumihalcea111@...il.com>
Cc: Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: imx: add dts for the imx8ulp evk9 board
On Mon, Jun 23, 2025 at 11:01:46AM -0400, Laurentiu Mihalcea wrote:
> From: Laurentiu Mihalcea <laurentiu.mihalcea@....com>
>
> Add DTS for the i.MX8ULP EVK9 board.
>
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@....com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 68 +++++++++++++++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 4da7501ece17..4b288b324d38 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
>
> imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts
> new file mode 100644
> index 000000000000..c610ec9aa30e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8ulp-evk.dts"
> +
> +/ {
> + model = "NXP i.MX8ULP EVK9";
It is new board, need compatible string for it. please update binding doc
also.
> +};
> +
> +&btcpu {
> + sound-dai = <&sai6>;
> +};
> +
> +&iomuxc1 {
> + pinctrl_sai6: sai6grp {
> + fsl,pins = <
> + MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43
> + MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43
> + MX8ULP_PAD_PTE14__I2S6_TXD2 0x43
> + MX8ULP_PAD_PTE6__I2S6_RXD0 0x43
> + >;
> + };
> +};
> +
> +&pinctrl_enet {
> + fsl,pins = <
> + MX8ULP_PAD_PTF9__ENET0_MDC 0x43
> + MX8ULP_PAD_PTF8__ENET0_MDIO 0x43
> + MX8ULP_PAD_PTF5__ENET0_RXER 0x43
> + MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43
> + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
> + MX8ULP_PAD_PTF0__ENET0_RXD1 0x43
> + MX8ULP_PAD_PTF4__ENET0_TXEN 0x43
> + MX8ULP_PAD_PTF3__ENET0_TXD0 0x43
> + MX8ULP_PAD_PTF2__ENET0_TXD1 0x43
> + MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43
> + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
> + >;
> +};
> +
> +&pinctrl_usb1 {
> + fsl,pins = <
> + MX8ULP_PAD_PTE16__USB0_ID 0x10003
> + MX8ULP_PAD_PTE18__USB0_OC 0x10003
can you align these number to the same column?
Frank
> + >;
> +};
> +
> +&pinctrl_usb2 {
> + fsl,pins = <
> + MX8ULP_PAD_PTD23__USB1_ID 0x10003
> + MX8ULP_PAD_PTE20__USB1_OC 0x10003
> + >;
> +};
> +
> +&sai6 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_sai6>;
> + pinctrl-1 = <&pinctrl_sai6>;
> + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>;
> + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
> + assigned-clock-rates = <12288000>;
> + fsl,dataline = <1 0x01 0x04>;
> + status = "okay";
> +};
> --
> 2.34.1
>
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