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Message-Id: <b822d960e1600ddc218bed1f927cceb65a3ede40.1750747163.git.yan.kei.fong@altera.com>
Date: Tue, 24 Jun 2025 14:52:28 +0800
From: yankei.fong@...era.com
To: Dinh Nguyen <dinguyen@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS),
linux-kernel@...r.kernel.org (open list),
Matthew Gerlach <matthew.gerlach@...era.com>
Subject: [PATCH 4/4] arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
From: "Fong, Yan Kei" <yan.kei.fong@...era.com>
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex5 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@...era.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@...era.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..853e260c3976 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -57,6 +57,8 @@ flash@0 {
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
--
2.25.1
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