linux-kernel - 回覆: 回覆: [PATCH 0/7] Add ASPEED PCIe Root Complex support

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Message-ID:
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Date: Tue, 24 Jun 2025 10:54:51 +0000
From: Jacky Chou <jacky_chou@...eedtech.com>
To: Neil Armstrong <neil.armstrong@...aro.org>, "bhelgaas@...gle.com"
	<bhelgaas@...gle.com>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kwilczynski@...nel.org" <kwilczynski@...nel.org>, "mani@...nel.org"
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	<andrew@...econstruct.com.au>, "vkoul@...nel.org" <vkoul@...nel.org>,
	"kishon@...nel.org" <kishon@...nel.org>, "linus.walleij@...aro.org"
	<linus.walleij@...aro.org>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "linux-aspeed@...ts.ozlabs.org"
	<linux-aspeed@...ts.ozlabs.org>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "devicetree@...r.kernel.org"
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	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-phy@...ts.infradead.org"
	<linux-phy@...ts.infradead.org>, "openbmc@...ts.ozlabs.org"
	<openbmc@...ts.ozlabs.org>, "linux-gpio@...r.kernel.org"
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CC: "elbadrym@...gle.com" <elbadrym@...gle.com>, "romlem@...gle.com"
	<romlem@...gle.com>, "anhphan@...gle.com" <anhphan@...gle.com>,
	"wak@...gle.com" <wak@...gle.com>, "yuxiaozhang@...gle.com"
	<yuxiaozhang@...gle.com>, BMC-SW <BMC-SW@...eedtech.com>
Subject:
 回覆: 回覆: [PATCH 0/7] Add ASPEED PCIe Root Complex support

> >>
> >> So it seems all PCIe RC code is bundled in a single driver and
> >> there's no PCIe PHY driver code, is there a reason for that ? If yes
> >> I think it should be described in the cover letter.
> >>
> >
> > Yes, because our design includes the PCIe RC and the PCIe EPs.
> > The two functions use the same PCIe PHY and are mutually exclusive.
> > And there are different configurations on RC and EP.
> > Therefore, we do not use a phy driver to configure our PCIe but use
> > the phandle of phy syscon to set the RC and EP drivers separately.
> 
> I don't get why a PHY drive could not exist, it could be used by either the RC or
> EP PCIe driver in an exclusive way.
> 

In our design, the configuration of pcie phy layer is set by HW default 
value. Therefore, we do not need to configure this part by software.
The aspeed,pcie-phy node is used to get some information like
link status, BDF number and the most important is we use it to
configure to EP or RC mode. As I said, our PCIe design existed EP
and RC and it uses the same PCIe PHY on HW. Maybe there is better
naming for this node.
Eventually, I think I don't need a PHY driver for complicated configuration.

Thanks,
Jacky