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Message-ID: <xkvn3r7yphlccurdqzncz5qegs7xc254xc2ou2dzuilatk5f5j@eq5ynce4aepg>
Date: Wed, 25 Jun 2025 14:36:54 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Taniya Das <quic_tdas@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock
node
On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support CPU frequency scaling.
>
> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
> qcom,remote-pid = <2>;
> };
> };
> +
> + cpufreq_hw: cpufreq@...23000 {
> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
Why? Other platforms use a true SoC as the first entry.
> + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
> + reg-names = "freq-domain0", "freq-domain1";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> + };
> +
> };
>
> arch_timer: timer {
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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