linux-kernel - [PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250625-p8700-pause-v4-3-6c7dd7f85756@htecgroup.com>
Date: Wed, 25 Jun 2025 16:20:58 +0200
From: Aleksa Paunovic via B4 Relay <devnull+aleksa.paunovic.htecgroup.com@...nel.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>, Jonathan Corbet <corbet@....net>
Cc: Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>, 
 devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, 
 linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, 
 Aleksa Paunovic <aleksa.paunovic@...cgroup.com>
Subject: [PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

From: Aleksa Paunovic <aleksa.paunovic@...cgroup.com>

Add MIPS.PAUSE instruction opcode. This instruction is a part of the
xmipsexectl vendor extension.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@...cgroup.com>
---
 arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe95987105ed85a 100644
--- a/arch/riscv/include/asm/vendor_extensions/mips.h
+++ b/arch/riscv/include/asm/vendor_extensions/mips.h
@@ -13,4 +13,11 @@
 
 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
 
+/* MIPS.PAUSE is an alternative opcode which is implemented to have the */
+/* same behavior as PAUSE on some MIPS RISCV cores. */
+/* It is a ‘hint’ encoding of the SLLI instruction, */
+/* with rd = 0, rs1 = 0 and imm = 5. */
+
+#define MIPS_PAUSE	".4byte 0x00501013\n\t"
+
 #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H

-- 
2.34.1