linux-kernel - Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <3514a3af-ab7d-41e6-9e59-95defe9105b4@oss.qualcomm.com>
Date: Wed, 25 Jun 2025 11:25:51 +0530
From: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE


On 6/24/2025 8:08 PM, Konrad Dybcio wrote:
> On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
>> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
>> first SE, which supports a 4-wire UART configuration suitable for
>> applications such as HS-UART.
>>
>> Note that the required initialization for this SE is not handled by the
>> bootloader. Therefore, add the SE node in the device tree but keep it
>> disabled. Enable it once Linux gains support for configuring the SE,
>> allowing to use in relevant RDPs.
> Do you mean fw loading support?

SE0 is minicore, so we don't need to load the FW. But apart from FW , 
protocol specific configurations to be done in the SE's Image 
Configuration registers, which is taken care in the patch[1]

[1] [PATCH v5 0/5] Add support to load QUP SE firmware from 
<https://lore.kernel.org/linux-arm-msm/20250624095102.1587580-1-viken.dadhaniya@oss.qualcomm.com/T/#m37a6b739c66040cde5b6b0121a03da7ea6715842>

>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@....qualcomm.com>
>> ---
>> Changes in v2:
>> - Correct the interrupt number
>> - Link to v1: https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.qualcomm.com
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c189bafe690514 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -417,6 +417,15 @@ qupv3: geniqup@...0000 {
>>   			#address-cells = <2>;
>>   			#size-cells = <2>;
>>   
>> +			uart0: serial@...0000 {
>> +				compatible = "qcom,geni-uart";
>> +				reg = <0 0x01a80000 0 0x4000>;
>> +				clocks = <&gcc GCC_QUPV3_UART0_CLK>;
>> +				clock-names = "se";
>> +				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
> I'd normally expect to see a pin configuration here as well,
> especially since you mention the bootloader doesn't configure
> the interface

Ack.

>
> Konrad