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Message-Id: <20250625082927.31038-9-quic_pkumpatl@quicinc.com>
Date: Wed, 25 Jun 2025 13:59:26 +0530
From: Prasad Kumpatla <quic_pkumpatl@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Srinivas Kandagatla <srini@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-sound@...r.kernel.org,
quic_pkumpatl@...cinc.com, kernel@....qualcomm.com,
Mohammad Rafi Shaik <quic_mohs@...cinc.com>
Subject: [PATCH v5 8/9] arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
From: Mohammad Rafi Shaik <quic_mohs@...cinc.com>
Add nodes for WSA8830 speakers and WCD9370 headset codec
on qcm6490-idp board.
Enable lpass macros along with audio support pin controls.
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@...cinc.com>
Co-developed-by: Prasad Kumpatla <quic_pkumpatl@...cinc.com>
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 123 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +++
2 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index 7a155ef6492e..468f5f9c0779 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -18,6 +18,7 @@
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
+#include "qcs6490-audioreach.dtsi"
/delete-node/ &ipa_fw_mem;
/delete-node/ &rmtfs_mem;
@@ -169,6 +170,30 @@ vph_pwr: vph-pwr-regulator {
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
+
+ wcd9370: audio-codec-0 {
+ compatible = "qcom,wcd9370-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+
+ vdd-buck-supply = <&vreg_l17b_1p7>;
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-px-supply = <&vreg_l18b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob_3p296>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+
+ qcom,rx-device = <&wcd937x_rx>;
+ qcom,tx-device = <&wcd937x_tx>;
+
+ #sound-dai-cells = <1>;
+ };
};
&apps_rsc {
@@ -536,6 +561,22 @@ &gpu_zap_shader {
firmware-name = "qcom/qcm6490/a660_zap.mbn";
};
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_va_macro {
+ status = "okay";
+};
+
+&lpass_wsa_macro {
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
@@ -716,6 +757,81 @@ &sdhc_2 {
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
};
+&swr0 {
+ status = "okay";
+
+ wcd937x_rx: codec@0,4 {
+ compatible = "sdw20217010a00";
+ reg = <0 4>;
+
+ /*
+ * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
+ * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
+ * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
+ * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
+ * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+
+ /*
+ * Static channels mapping between slave and master rx port channels.
+ * In the order of slave port channels, which is
+ * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l.
+ */
+ qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd937x_tx: codec@0,3 {
+ compatible = "sdw20217010a00";
+ reg = <0 3>;
+
+ /*
+ * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
+ * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
+ * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
+ * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
+ */
+ qcom,tx-port-mapping = <1 1 2 3>;
+
+ /*
+ * Static channel mapping between slave and master tx port channels.
+ * In the order of slave port channels which is adc1, adc2, adc3,
+ * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7.
+ */
+ qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ left_spkr: speaker@0,1 {
+ compatible = "sdw10217020200";
+ reg = <0 1>;
+ powerdown-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ #thermal-sensor-cells = <0>;
+ vdd-supply = <&vreg_l18b_1p8>;
+ qcom,port-mapping = <1 2 3 7>;
+ };
+
+ right_spkr: speaker@0,2 {
+ compatible = "sdw10217020200";
+ reg = <0 2>;
+ powerdown-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ #thermal-sensor-cells = <0>;
+ vdd-supply = <&vreg_l18b_1p8>;
+ qcom,port-mapping = <4 5 6 8>;
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
@@ -725,6 +841,13 @@ sd_cd: sd-cd-state {
function = "gpio";
bias-pull-up;
};
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
&uart5 {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fff92fd836ab..b9cca45a5fb2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2898,21 +2898,33 @@ lpass_dmic23_data: dmic23-data-state {
lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
};
lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
};
lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
};
lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
};
lpass_wsa_swr_clk: wsa-swr-clk-state {
--
2.34.1
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