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Message-ID: <20250625084709.3968844-1-r09922117@csie.ntu.edu.tw>
Date: Wed, 25 Jun 2025 16:47:09 +0800
From: Wei-Lin Chang <r09922117@...e.ntu.edu.tw>
To: linux-arm-kernel@...ts.infradead.org,
	kvmarm@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Cc: Marc Zyngier <maz@...nel.org>,
	Oliver Upton <oliver.upton@...ux.dev>,
	Joey Gouly <joey.gouly@....com>,
	Suzuki K Poulose <suzuki.poulose@....com>,
	Zenghui Yu <yuzenghui@...wei.com>,
	Catalin Marinas <catalin.marinas@....com>,
	Wei-Lin Chang <r09922117@...e.ntu.edu.tw>,
	Will Deacon <will@...nel.org>,
	Jintack Lim <jintack@...columbia.edu>,
	Christoffer Dall <christoffer.dall@....com>
Subject: [PATCH] KVM: arm64: nv: Fix MI line level calculation in vgic_v3_nested_update_mi()

The state of the vcpu's MI line should be asserted when its
ICH_HCR_EL2.En is set and ICH_MISR_EL2 is non-zero. Using bitwise AND
(&=) directly for this calculation will not give us the correct result
when the LSB of the vcpu's ICH_MISR_EL2 isn't set. Correct this by first
adjusting the return value of vgic_v3_get_misr() into 1 if it is
non-zero.

Signed-off-by: Wei-Lin Chang <r09922117@...e.ntu.edu.tw>
---
 arch/arm64/kvm/vgic/vgic-v3-nested.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
index 4f6954c30674..ebffad632fd2 100644
--- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
+++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
@@ -400,7 +400,7 @@ void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu)
 
 	level  = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En;
 	if (level)
-		level &= vgic_v3_get_misr(vcpu);
+		level &= !!vgic_v3_get_misr(vcpu);
 	kvm_vgic_inject_irq(vcpu->kvm, vcpu,
 			    vcpu->kvm->arch.vgic.mi_intid, level, vcpu);
 }
-- 
2.49.0


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