linux-kernel - [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties

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Message-Id: <20250625085801.526669-4-quic_ziyuzhan@quicinc.com>
Date: Wed, 25 Jun 2025 16:58:01 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
        krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
        mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
        bhelgaas@...gle.com, johan+linaro@...nel.org, vkoul@...nel.org,
        kishon@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
        kw@...ux.com
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
        quic_krichai@...cinc.com, quic_vbadigan@...cinc.com,
        Ziyue Zhang <quic_ziyuzhan@...cinc.com>,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH v3 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties

Add PCIe lane equalization preset properties with all values set to 5 for
8.0 GT/s and 16.0 GT/s data rates to enhance link stability.

Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 45f536633f64..16caf1da0708 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7159,6 +7159,9 @@ pcie0: pcie@...0000 {
 		phys = <&pcie0_phy>;
 		phy-names = "pciephy";
 
+		eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+		eq-presets-16gts = /bits/ 8 <0x55 0x55>;
+
 		status = "disabled";
 
 		pcieport0: pcie@0 {
@@ -7317,6 +7320,9 @@ pcie1: pcie@...0000 {
 		phys = <&pcie1_phy>;
 		phy-names = "pciephy";
 
+		eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+		eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
 		status = "disabled";
 
 		pcie@0 {
-- 
2.34.1