linux-kernel - [tip: irq/drivers] dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi

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Message-ID: <175094718853.406.964028946511027482.tip-bot2@tip-bot2>
Date: Thu, 26 Jun 2025 14:13:08 -0000
From: "tip-bot2 for Vladimir Kondratiev" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
 Thomas Gleixner <tglx@...utronix.de>,
 Conor Dooley <conor.dooley@...rochip.com>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject: [tip: irq/drivers] dt-bindings: interrupt-controller: Add MIPS P8700
 aclint-sswi

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     ed651979bb780270ae14b35ca6bae68f658eddad
Gitweb:        https://git.kernel.org/tip/ed651979bb780270ae14b35ca6bae68f658eddad
Author:        Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
AuthorDate:    Thu, 12 Jun 2025 17:39:07 +03:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Thu, 26 Jun 2025 16:06:40 +02:00

dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi

Add ACLINT-SSWI variant for the MIPS P8700 SoC. This CPU has a SSWI device
compliant with the RISC-V draft spec (see [1]).

CPU indexes on this platform are not continuous, instead it uses bit-fields
to encode hart,core,cluster numbers, thus the DT property
"riscv,hart-indexes" is mandatory for it.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Link: https://lore.kernel.org/all/20250612143911.3224046-4-vladimir.kondratiev@mobileye.com
Link: https://github.com/riscvarchive/riscv-aclint [1]


---
 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 55 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
index 8d33090..c1ab865 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -4,23 +4,32 @@
 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device
+title: ACLINT Supervisor-level Software Interrupt Device
 
 maintainers:
   - Inochi Amaoto <inochiama@...look.com>
 
 description:
-  The SSWI device is a part of the THEAD ACLINT device. It provides
-  supervisor-level IPI functionality for a set of HARTs on a THEAD
-  platform. It provides a register to set an IPI (SETSSIP) for each
-  HART connected to the SSWI device.
+  The SSWI device is a part of the ACLINT device. It provides
+  supervisor-level IPI functionality for a set of HARTs on a supported
+  platforms. It provides a register to set an IPI (SETSSIP) for each
+  HART connected to the SSWI device. See draft specification
+  https://github.com/riscvarchive/riscv-aclint
+
+  Following variants of the SSWI ACLINT supported, using dedicated
+  compatible string
+  - THEAD C900
+  - MIPS P8700
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sophgo,sg2044-aclint-sswi
-      - const: thead,c900-aclint-sswi
+    oneOf:
+      - items:
+          - enum:
+              - sophgo,sg2044-aclint-sswi
+          - const: thead,c900-aclint-sswi
+      - items:
+          - const: mips,p8700-aclint-sswi
 
   reg:
     maxItems: 1
@@ -34,6 +43,14 @@ properties:
     minItems: 1
     maxItems: 4095
 
+  riscv,hart-indexes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4095
+    description:
+      A list of hart indexes that APLIC should use to address each hart
+      that is mentioned in the "interrupts-extended"
+
 additionalProperties: false
 
 required:
@@ -43,8 +60,22 @@ required:
   - interrupt-controller
   - interrupts-extended
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mips,p8700-aclint-sswi
+    then:
+      required:
+        - riscv,hart-indexes
+    else:
+      properties:
+        riscv,hart-indexes: false
+
 examples:
   - |
+    //Example 1
     interrupt-controller@...00000 {
       compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
       reg = <0x94000000 0x00004000>;
@@ -55,4 +86,19 @@ examples:
                             <&cpu3intc 1>,
                             <&cpu4intc 1>;
     };
+
+  - |
+    //Example 2
+    interrupt-controller@...00000 {
+      compatible = "mips,p8700-aclint-sswi";
+      reg = <0x94000000 0x00004000>;
+      #interrupt-cells = <0>;
+      interrupt-controller;
+      interrupts-extended = <&cpu1intc 1>,
+                            <&cpu2intc 1>,
+                            <&cpu3intc 1>,
+                            <&cpu4intc 1>;
+      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
+    };
+
 ...