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Message-Id: <20250626195610.405379-13-kan.liang@linux.intel.com>
Date: Thu, 26 Jun 2025 12:56:09 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
mark.rutland@....com,
broonie@...nel.org,
ravi.bangoria@....com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH V2 12/13] perf/x86: Add SSP into sample_regs
From: Kan Liang <kan.liang@...ux.intel.com>
The SSP is only supported when the new SIMD registers configuration
method is used, which moves the XMM to sample_simd_vec_regs. So the
space can be reclaimed for the SSP.
The SSP is retrieved by XSAVE. Only support the SSP for X86_64.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 16 +++++++++++++++-
arch/x86/events/perf_event.h | 1 +
arch/x86/include/asm/perf_event.h | 4 ++++
arch/x86/include/uapi/asm/perf_regs.h | 3 +++
arch/x86/kernel/perf_regs.c | 8 +++++++-
5 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 1da18886e1f3..b35b5695e42f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -431,6 +431,8 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
perf_regs->opmask = get_xsave_addr(xsave, XFEATURE_OPMASK);
if (mask & XFEATURE_MASK_APX)
perf_regs->egpr = get_xsave_addr(xsave, XFEATURE_APX);
+ if (mask & XFEATURE_MASK_CET_USER)
+ perf_regs->cet = get_xsave_addr(xsave, XFEATURE_CET_USER);
}
static void release_ext_regs_buffers(void)
@@ -467,6 +469,8 @@ static void reserve_ext_regs_buffers(void)
mask |= XFEATURE_MASK_OPMASK;
if (x86_pmu.ext_regs_mask & X86_EXT_REGS_EGPRS)
mask |= XFEATURE_MASK_APX;
+ if (x86_pmu.ext_regs_mask & X86_EXT_REGS_CET)
+ mask |= XFEATURE_MASK_CET_USER;
size = xstate_calculate_size(mask, true);
@@ -723,7 +727,7 @@ int x86_pmu_hw_config(struct perf_event *event)
if (event->attr.sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) {
if (event->attr.sample_simd_regs_enabled) {
- u64 reserved = ~GENMASK_ULL(PERF_REG_X86_64_MAX - 1, 0);
+ u64 reserved = ~GENMASK_ULL(PERF_REG_MISC_MAX - 1, 0);
if (!(event->pmu->capabilities & PERF_PMU_CAP_SIMD_REGS))
return -EINVAL;
@@ -738,6 +742,11 @@ int x86_pmu_hw_config(struct perf_event *event)
event->attr.sample_regs_intr & PERF_X86_EGPRS_MASK) &&
!(x86_pmu.ext_regs_mask & X86_EXT_REGS_EGPRS))
return -EINVAL;
+ if ((event->attr.sample_regs_user & BIT_ULL(PERF_REG_X86_SSP) ||
+ event->attr.sample_regs_intr & BIT_ULL(PERF_REG_X86_SSP)) &&
+ !(x86_pmu.ext_regs_mask & X86_EXT_REGS_CET))
+ return -EINVAL;
+
} else {
/*
* Besides the general purpose registers, XMM registers may
@@ -1915,6 +1924,11 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
perf_regs->egpr_regs = NULL;
mask |= XFEATURE_MASK_APX;
}
+ if (attr->sample_regs_user & BIT_ULL(PERF_REG_X86_SSP) ||
+ attr->sample_regs_intr & BIT_ULL(PERF_REG_X86_SSP)) {
+ perf_regs->cet_regs = NULL;
+ mask |= XFEATURE_MASK_CET_USER;
+ }
}
mask &= ~ignore_mask;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 4dd1e7344021..1d958059db07 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -706,6 +706,7 @@ enum {
X86_EXT_REGS_H16ZMM = BIT_ULL(3),
X86_EXT_REGS_OPMASK = BIT_ULL(4),
X86_EXT_REGS_EGPRS = BIT_ULL(5),
+ X86_EXT_REGS_CET = BIT_ULL(6),
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4400cb66bc8e..28ddff38d232 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -617,6 +617,10 @@ struct x86_perf_regs {
u64 *egpr_regs;
struct apx_state *egpr;
};
+ union {
+ u64 *cet_regs;
+ struct cet_user_state *cet;
+ };
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index cd0f6804debf..4d88cb18acb9 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -48,6 +48,9 @@ enum perf_event_x86_regs {
PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
PERF_REG_X86_64_MAX = PERF_REG_X86_R31 + 1,
+ PERF_REG_X86_SSP,
+ PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1,
+
/*
* These all need two bits set because they are 128bit.
* These are only available when !PERF_SAMPLE_REGS_ABI_SIMD
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 3780a7b0e021..f985765a799a 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -70,6 +70,11 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
return 0;
return perf_regs->egpr_regs[idx - PERF_REG_X86_R16];
}
+ if (idx == PERF_REG_X86_SSP) {
+ if (!perf_regs->cet_regs)
+ return 0;
+ return perf_regs->cet_regs[1];
+ }
} else {
if (idx >= PERF_REG_X86_XMM0 && idx < PERF_REG_X86_XMM_MAX) {
if (!perf_regs->xmm_regs)
@@ -157,7 +162,8 @@ int perf_simd_reg_validate(u16 vec_qwords, u64 vec_mask,
~((1ULL << PERF_REG_X86_MAX) - 1))
#ifdef CONFIG_X86_32
-#define REG_NOSUPPORT GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R8)
+#define REG_NOSUPPORT (GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R8) | \
+ BIT_ULL(PERF_REG_X86_SSP))
int perf_reg_validate(u64 mask)
{
--
2.38.1
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