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Message-ID: <20250626220148.GR17294@gate.crashing.org>
Date: Thu, 26 Jun 2025 17:01:48 -0500
From: Segher Boessenkool <segher@...nel.crashing.org>
To: Christophe Leroy <christophe.leroy@...roup.eu>
Cc: David Laight <david.laight.linux@...il.com>,
Michael Ellerman <mpe@...erman.id.au>,
Nicholas Piggin <npiggin@...il.com>, Naveen N Rao <naveen@...nel.org>,
Madhavan Srinivasan <maddy@...ux.ibm.com>,
Alexander Viro <viro@...iv.linux.org.uk>,
Christian Brauner <brauner@...nel.org>, Jan Kara <jack@...e.cz>,
Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
Peter Zijlstra <peterz@...radead.org>,
Darren Hart <dvhart@...radead.org>,
Davidlohr Bueso <dave@...olabs.net>,
Andre Almeida <andrealmeid@...lia.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
linux-fsdevel@...r.kernel.org, linux-mm@...ck.org
Subject: Re: [PATCH 0/5] powerpc: Implement masked user access
On Thu, Jun 26, 2025 at 07:56:10AM +0200, Christophe Leroy wrote:
> Le 24/06/2025 à 23:08, David Laight a écrit :
> >On Tue, 24 Jun 2025 13:25:05 -0500
> >Segher Boessenkool <segher@...nel.crashing.org> wrote:
> >>>>isel (which is base PowerPC, not something "e500" only) is a
> >>>>computational instruction, it copies one of two registers to a third,
> >>>>which of the two is decided by any bit in the condition register.
> >>>
> >>>Does that mean it could be used for all the ppc cpu variants?
> >>
> >>No, only things that implement architecture version of 2.03 or later.
> >>That is from 2006, so essentially everything that is still made
> >>implements it :-)
> >>
> >>But ancient things do not. Both 970 (Apple G5) and Cell BE do not yet
> >>have it (they are ISA 2.01 and 2.02 respectively). And the older p5's
> >>do not have it yet either, but the newer ones do.
>
> For book3s64, GCC only use isel with -mcpu=power9 or -mcpu=power10
I have no idea what "book3s64" means.
Some ancient Power architecture versions had something called
"Book III-S", which was juxtaposed to "Book III-E", which essentially
corresponds to the old aborted BookE stuff.
I guess you mean almost all non-FSL implementations? Most of those
support the isel insns. Like, Power5+ (GS). And everything after that.
I have no idea why you think power9 has it while older CPUS do not. In
the GCC source code we have this comment:
/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
and in fact we do not enable it for ISA 2.06 (p8) either, probably for
a similar reason.
> >>And all classic PowerPC is ISA 1.xx of course. Medieval CPUs :-)
> >
> >That make more sense than the list in patch 5/5.
>
> Sorry for the ambiguity. In patch 5/5 I was addressing only powerpc/32,
> and as far as I know the only powerpc/32 supported by Linux that has
> isel is the 85xx which has an e500 core.
What is "powerpc/32"? It does not help if you use different names from
what everyone else does.
The name "powerpc32" is sometimes used colloquially to mean PowerPC code
running in SF=0 mode (MSR[SF]=0), but perhaps more often it is used for
32-bit only implementations (so, those that do not even have that bit:
it's bit 0 in the 64-bit MSR, so all implementations that have an only
32-bit MSR, for example).
> For powerpc/64 we have less constraint than on powerpc32:
> - Kernel memory starts at 0xc000000000000000
> - User memory stops at 0x0010000000000000
That isn't true, not even if you mean some existing name. Usually
userspace code is mapped at 256MB (0x10000000). On powerpc64-linux
anyway, different default on different ABIs of course :-)
> >And for access_ok() avoiding the conditional is a good enough reason
> >to use a 'conditional move' instruction.
> >Avoiding speculation is actually free.
>
> And on CPUs that are not affected by Spectre and Meltdown like powerpc
> 8xx or powerpc 603,
Erm.
Segher
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