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Message-ID: <20250626224336.867412-1-seanjc@google.com>
Date: Thu, 26 Jun 2025 15:43:36 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Paolo Bonzini <pbonzini@...hat.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
Sean Christopherson <seanjc@...gle.com>
Subject: [kvm-unit-tests GIT PULL] x86: Fixes, cleanups, and new testcases
Please pull a self-centered set of KUT changes.
The following changes since commit 507612326c9417b6330b91f7931678a4c6866395:
travis.yml: Remove the aarch64 job (2025-06-05 10:07:07 +0200)
are available in the Git repository at:
https://github.com/kvm-x86/kvm-unit-tests.git tags/kvm-x86-2025.06.26
for you to fetch changes up to 525bdb5d65d51a367341f471eb1bcd505d73c51f:
x86/pmu: Verify all available GP counters in check_counters_many() (2025-06-25 14:20:34 -0700)
----------------------------------------------------------------
x86 fixes, cleanups, and new test coverage
- Ensure APIC is xAPIC mode for APIC MMIO tests.
- Expand the I/O APIC routing reconfiguration vs. EOI interception testcase
to validate multiple in-flight interrupts.
- Fix a variety of minor PMU/PEBS bugs and warts.
- Fix the nSVM MSR interception test to actually detect failures, and expand
its coverage to validate more scenarios.
- Add X86_PROPERTY_xxx macros (stolen from KVM selftests) and use them to
clean up related code.
- Add testcases for MSR_SPEC_CTRL, and an msr64 config to validate negative
testcases (i.e. when MSRs aren't supposed to exist).
- Disable PIT re-injection for all tests so that (x2)AVIC isn't inhibited due
to enabling in-kernel PIT emulation.
- Play nice with QEMU builds that disable VNX support.
----------------------------------------------------------------
Dapeng Mi (2):
x86/pmu_pebs: Initalize and enable PMU interrupt (PMI_VECTOR)
x86/pmu: Verify all available GP counters in check_counters_many()
Sean Christopherson (41):
x86: apic: Move helpers for querying APIC state to library code
x86: nSVM: Ensure APIC MMIO tests run with APIC in xAPIC mode
x86: ioapic: Expand routing reconfiguration => EOI interception testcase
runtime: Skip tests if the target "kernel" file doesn't exist
x86/pks: Actually skip the PKS test if PKS isn't support
x86/pmu: Explicitly zero PERF_GLOBAL_CTRL at start of PMU test
x86/run: Specify "-vnc none" for QEMU if and only if QEMU supports VNC
lib: Add and use static_assert() convenience wrappers
x86: Call setup_idt() from start{32,64}(), not from smp_init()
x86: Drop protection against setup_idt() being called multiple times
x86: Move call to load_idt() out of setup_tr_and_percpu macro
x86: Load IDT on BSP as part of setup_idt()
x86: Cache availability of forced emulation during setup_idt()
nVMX: Force emulation of LGDT/LIDT in iff FEP is available
x86: nSVM: Actually report missed MSR intercepts as failures
x86: nSVM: Test MSRs just outside the ranges of the MSR Permissions Map
x86: nSVM: Clean up variable types and names in test_msr_intercept()
x86: Expand the suite of bitops to cover all set/clear operations
x86: nVMX: Use set_bit() instead of test_and_set_bit() when return is ignored
x86: nSVM: Set MSRPM bit on-demand when testing interception
x86: nSVM: Verify disabling {RD,WR}MSR interception behaves as expected
x86: nSVM: Verify L1 and L2 see same MSR value when interception is disabled
x86: Disable PIT re-injection for all tests to play nice with (x2)AVIC
x86: Delete split IRQ chip variants of apic and ioapic tests
x86: Encode X86_FEATURE_* definitions using a structure
x86: Add X86_PROPERTY_* framework to retrieve CPUID values
x86: Use X86_PROPERTY_MAX_VIRT_ADDR in is_canonical()
x86: Implement get_supported_xcr0() using X86_PROPERTY_SUPPORTED_XCR0_{LO,HI}
x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES
x86/pmu: Mark all arch events as available on AMD, and rename fields
x86/pmu: Mark Intel architectural event available iff X <= CPUID.0xA.EAX[31:24]
x86/pmu: Use X86_PROPERTY_PMU_* macros to retrieve PMU information
x86/sev: Use VC_VECTOR from processor.h
x86/sev: Skip the AMD SEV test if SEV is unsupported/disabled
x86/sev: Define and use X86_FEATURE_* flags for CPUID 0x8000001F
x86/sev: Use X86_PROPERTY_SEV_C_BIT to get the AMD SEV C-bit location
x86/sev: Use amd_sev_es_enabled() to detect if SEV-ES is enabled
x86: Move SEV MSR definitions to msr.h
x86/msr: Treat PRED_CMD as support if CPU has SBPB
x86/msr: Add a testcase to verify SPEC_CTRL exists (or not) as expected
x86/msr: Add an "msr64" test configuration to validate negative cases
lib/riscv/asm/isa.h | 4 +-
lib/s390x/asm/arch_def.h | 6 +-
lib/s390x/fault.c | 3 +-
lib/util.h | 3 +
lib/x86/amd_sev.c | 48 ++-----
lib/x86/amd_sev.h | 29 -----
lib/x86/apic.h | 21 +++
lib/x86/asm/bitops.h | 86 +++++++++++-
lib/x86/desc.c | 29 ++++-
lib/x86/desc.h | 14 +-
lib/x86/msr.h | 14 +-
lib/x86/pmu.c | 25 ++--
lib/x86/pmu.h | 8 +-
lib/x86/processor.h | 332 +++++++++++++++++++++++++++++++++--------------
lib/x86/setup.c | 1 -
lib/x86/smp.c | 1 -
scripts/runtime.bash | 5 +
x86/access.c | 2 +-
x86/amd_sev.c | 63 ++-------
x86/apic.c | 20 ---
x86/cstart.S | 3 +-
x86/cstart64.S | 2 +-
x86/emulator.c | 11 +-
x86/emulator64.c | 2 +-
x86/ioapic.c | 52 +++++++-
x86/la57.c | 4 +-
x86/lam.c | 6 +-
x86/msr.c | 36 ++++-
x86/pks.c | 2 +-
x86/pmu.c | 37 ++++--
x86/pmu_pebs.c | 3 +
x86/run | 15 ++-
x86/svm_npt.c | 27 ++++
x86/svm_tests.c | 240 ++++++++++++++++++++++++++--------
x86/unittests.cfg | 30 ++---
x86/vmx_tests.c | 11 +-
x86/xsave.c | 11 +-
37 files changed, 792 insertions(+), 414 deletions(-)
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