linux-kernel - Re: [PATCH RESEND] dmaengine: stm32-dma: configure next sg only if there are more than 2 sgs

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Message-Id: <175097808959.79884.12989914478900786264.b4-ty@kernel.org>
Date: Thu, 26 Jun 2025 15:48:09 -0700
From: Vinod Koul <vkoul@...nel.org>
To: Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Amelie Delaunay <amelie.delaunay@...s.st.com>
Cc: dmaengine@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND] dmaengine: stm32-dma: configure next sg only if
 there are more than 2 sgs


On Tue, 24 Jun 2025 09:31:37 +0200, Amelie Delaunay wrote:
> DMA operates in Double Buffer Mode (DBM) when the transfer is cyclic and
> there are at least two periods.
> When DBM is enabled, the DMA toggles between two memory targets (SxM0AR and
> SxM1AR), indicated by the SxSCR.CT bit (Current Target).
> There is no need to update the next memory address if two periods are
> configured, as SxM0AR and SxM1AR are already properly set up before the
> transfer begins in the stm32_dma_start_transfer() function.
> This avoids unnecessary updates to SxM0AR/SxM1AR, thereby preventing
> potential Transfer Errors. Specifically, when the channel is enabled,
> SxM0AR and SxM1AR can only be written if SxSCR.CT=1 and SxSCR.CT=0,
> respectively. Otherwise, a Transfer Error interrupt is triggered, and the
> stream is automatically disabled.
> 
> [...]

Applied, thanks!

[1/1] dmaengine: stm32-dma: configure next sg only if there are more than 2 sgs
      commit: e19bdbaa31082b43dab1d936e20efcebc30aa73d

Best regards,
-- 
~Vinod