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Message-ID: <b37efc4e-0959-47a0-8fae-6cb35899752e@ti.com>
Date: Thu, 26 Jun 2025 16:04:46 +0530
From: "Kumar, Udit" <u-kumar1@...com>
To: Jayesh Choudhary <j-choudhary@...com>, <nm@...com>, <vigneshr@...com>,
<devicetree@...r.kernel.org>
CC: <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devarsht@...com>, <u-kumar1@...com>
Subject: Re: [PATCH v2 6/7] arm64: dts: ti: k3-j721s2-common-proc-board:
Enable DisplayPort-1
On 6/24/2025 1:56 PM, Jayesh Choudhary wrote:
> Enable DSI display for J721S2 EVM.
>
> Add the endpoint nodes to describe connection from:
> DSS => DSI Bridge => DSI to eDP bridge => DisplayPort-1
>
> Set status for all required nodes for DisplayPort-1 as 'okay'.
>
> Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
> ---
> .../dts/ti/k3-j721s2-common-proc-board.dts | 89 +++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index 793d50344fad..efe857a50bb1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -93,6 +93,29 @@ vdd_sd_dv: gpio-regulator-TLV71033 {
> <3300000 0x1>;
> };
>
> + dp1_pwr_3v3: regulator-dp1-prw {
> + compatible = "regulator-fixed";
> + regulator-name = "dp1-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
> + enable-active-high;
> + regulator-always-on;
Please check once, if this regulator falls under regulator-always-on case,
I can imagine a case, where DP1 is not used and still regulator is kept on
> + };
> +
> + dp1: connector-dp1 {
> + compatible = "dp-connector";
> + label = "DP1";
> + type = "full-size";
> + dp-pwr-supply = <&dp1_pwr_3v3>;
> +
> + port {
> + dp1_connector_in: endpoint {
> + remote-endpoint = <&dp1_out>;
> + };
> + };
> + };
> +
> transceiver1: can-phy1 {
> compatible = "ti,tcan1043";
> #phy-cells = <0>;
> @@ -563,3 +586,69 @@ &main_mcan5 {
> pinctrl-0 = <&main_mcan5_pins_default>;
> phys = <&transceiver4>;
> };
> +
> +&dss {
> + /*
> + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2.
> + * These clock assignments are chosen to enable the following outputs:
> + * VP0 - DisplayPort SST
> + * VP2 - DSI
> + */
> + status = "okay";
> + assigned-clocks = <&k3_clks 158 2>,
> + <&k3_clks 158 14>;
> + assigned-clock-parents = <&k3_clks 158 3>,
> + <&k3_clks 158 16>;
> +};
> +
> +&dss_ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@2 {
> + reg = <2>;
> + dpi2_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +};
> +
> +&dsi0_ports {
> + port@0 {
> + reg = <0>;
> + dsi0_out: endpoint {
> + remote-endpoint = <&dp1_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpi2_out>;
> + };
> + };
> +};
> +
> +&dsi_edp_bridge_ports {
> + port@0 {
> + reg = <0>;
> + dp1_in: endpoint {
> + remote-endpoint = <&dsi0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dp1_out: endpoint {
> + remote-endpoint = <&dp1_connector_in>;
> + };
> + };
> +};
> +
> +&dphy_tx0 {
> + status = "okay";
> +};
> +
> +&dsi0 {
> + status = "okay";
> +};
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