linux-kernel - Re: [tip: x86/urgent] x86/traps: Initialize DR7 by writing its architectural reset value

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Message-ID: <aF1L0fbNL6xE0C8d@google.com>
Date: Thu, 26 Jun 2025 06:32:01 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Borislav Petkov <bp@...en8.de>
Cc: "Xin Li (Intel)" <xin@...or.com>, linux-kernel@...r.kernel.org, 
	linux-tip-commits@...r.kernel.org, Dave Hansen <dave.hansen@...ux.intel.com>, 
	"H. Peter Anvin (Intel)" <hpa@...or.com>, Sohil Mehta <sohil.mehta@...el.com>, 
	"Peter Zijlstra (Intel)" <peterz@...radead.org>, stable@...r.kernel.org, x86@...nel.org
Subject: Re: [tip: x86/urgent] x86/traps: Initialize DR7 by writing its
 architectural reset value

On Thu, Jun 26, 2025, Borislav Petkov wrote:
> On Tue, Jun 24, 2025 at 08:35:22PM -0000, tip-bot2 for Xin Li (Intel) wrote:
> > The following commit has been merged into the x86/urgent branch of tip:
> > 
> > Commit-ID:     fa7d0f83c5c4223a01598876352473cb3d3bd4d7
> > Gitweb:        https://git.kernel.org/tip/fa7d0f83c5c4223a01598876352473cb3d3bd4d7
> > Author:        Xin Li (Intel) <xin@...or.com>
> > AuthorDate:    Fri, 20 Jun 2025 16:15:04 -07:00
> > Committer:     Dave Hansen <dave.hansen@...ux.intel.com>
> > CommitterDate: Tue, 24 Jun 2025 13:15:52 -07:00
> > 
> > x86/traps: Initialize DR7 by writing its architectural reset value
> > 
> > Initialize DR7 by writing its architectural reset value to always set
> > bit 10, which is reserved to '1', when "clearing" DR7 so as not to
> > trigger unanticipated behavior if said bit is ever unreserved, e.g. as
> > a feature enabling flag with inverted polarity.
> 
> OMG, who wrote that "text"? 

I'm pretty sure I can take credit for the latter half.  You're welcome :-)