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Message-ID: <20250627204432.GA45217-robh@kernel.org>
Date: Fri, 27 Jun 2025 15:44:32 -0500
From: Rob Herring <robh@...nel.org>
To: Luca Weiss <luca.weiss@...rphone.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: document the SM7635 Top Level
 Mode Multiplexer

On Wed, Jun 25, 2025 at 11:12:01AM +0200, Luca Weiss wrote:
> Document the Top Level Mode Multiplexer on the SM7635 Platform.
> 
> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
> ---
>  .../bindings/pinctrl/qcom,sm7635-tlmm.yaml         | 133 +++++++++++++++++++++
>  1 file changed, 133 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm7635-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm7635-tlmm.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f49239efb6e866015b40e3477a8bd0edd21b1fc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm7635-tlmm.yaml
> @@ -0,0 +1,133 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sm7635-tlmm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. SM7635 TLMM block
> +
> +maintainers:
> +  - Luca Weiss <luca.weiss@...rphone.com>
> +
> +description:
> +  Top Level Mode Multiplexer pin controller in Qualcomm SM7635 SoC.
> +
> +allOf:
> +  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,sm7635-tlmm
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  gpio-reserved-ranges:
> +    minItems: 1
> +    maxItems: 84
> +
> +  gpio-line-names:
> +    maxItems: 167
> +
> +patternProperties:
> +  "-state$":
> +    oneOf:
> +      - $ref: "#/$defs/qcom-sm7635-tlmm-state"
> +      - patternProperties:
> +          "-pins$":
> +            $ref: "#/$defs/qcom-sm7635-tlmm-state"
> +        additionalProperties: false

Is there really value in continuing this complicated QCom pattern? Can 
we just have 1 level or 2 levels only?

> +
> +$defs:
> +  qcom-sm7635-tlmm-state:
> +    type: object
> +    description:
> +      Pinctrl node's client devices use subnodes for desired pin configuration.
> +      Client device subnodes use below standard properties.
> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +    unevaluatedProperties: false
> +
> +    properties:
> +      pins:
> +        description:
> +          List of gpio pins affected by the properties specified in this
> +          subnode.
> +        items:
> +          oneOf:
> +            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$"
> +            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
> +        minItems: 1
> +        maxItems: 36
> +
> +      function:
> +        description:
> +          Specify the alternative function to be configured for the specified
> +          pins.
> +        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
> +                audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0,
> +                cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx,
> +                coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
> +                ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot,
> +                egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0,
> +                i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
> +                mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
> +                mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n,
> +                pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
> +                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
> +                qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss,
> +                qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0,
> +                qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6,
> +                qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
> +                qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd,
> +                sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data,
> +                sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout,
> +                tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
> +                tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
> +                uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb,
> +                uim1_data_mira, uim1_data_mirb, uim1_present_mira,
> +                uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs,
> +                usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw,
> +                wcn_sw_ctrl ]
> +
> +    required:
> +      - pins
> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    tlmm: pinctrl@...0000 {
> +        compatible = "qcom,sm7635-tlmm";
> +        reg = <0x0f100000 0x300000>;
> +
> +        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +
> +        gpio-ranges = <&tlmm 0 0 168>;
> +
> +        gpio-wo-state {
> +            pins = "gpio1";
> +            function = "gpio";
> +        };
> +
> +        qup-uart5-default-state {
> +            pins = "gpio25", "gpio26";
> +            function = "qup0_se5";
> +            drive-strength = <2>;
> +            bias-disable;
> +        };

Please make the example more complete showing the multiple levels of 
states and pins if you are going to keep that.

Rob

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