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Message-ID: <20250627210526.GA128966-robh@kernel.org>
Date: Fri, 27 Jun 2025 16:05:26 -0500
From: Rob Herring <robh@...nel.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>,
Linus Walleij <linus.walleij@...aro.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
Bartosz Golaszewski <brgl@...ev.pl>,
linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: pinctrl: renesas: document RZ/T2H
and RZ/N2H SoCs
On Wed, Jun 25, 2025 at 02:07:10PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Document the pin and GPIO controller IP for the Renesas RZ/T2H
> (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI
> header file used by both the bindings and the driver.
>
> The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins.
> Both share the same controller architecture; separate compatible
> strings are added for each SoC to distinguish them.
>
> Co-developed-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v1->v2:
> - Added a new DT binding file
> ---
> .../pinctrl/renesas,rzt2h-pinctrl.yaml | 132 ++++++++++++++++++
> .../pinctrl/renesas,r9a09g077-pinctrl.h | 22 +++
> 2 files changed, 154 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> new file mode 100644
> index 000000000000..d3886eab93fe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/renesas,rzt2h-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/T2H Pin and GPIO controller
> +
> +maintainers:
> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> +
> +description:
> + The Renesas RZ/T2H SoC features a combined Pin and GPIO controller.
> + Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> + Each port features up to 8 pins, each of them configurable for GPIO function
> + (port mode) or in alternate function mode.
> + Up to 8 different alternate function modes exist for each single pin.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a09g077-pinctrl # RZ/T2H
> + - renesas,r9a09g087-pinctrl # RZ/N2H
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Non-safety I/O Port base
> + - description: Safety I/O Port safety region base
> + - description: Safety I/O Port Non-safety region base
> +
> + reg-names:
> + minItems: 1
> + items:
> + - const: nsr
> + - const: srs
> + - const: srn
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> + description:
> + The first cell contains the global GPIO port index, constructed using the
> + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
> + flag, as mentioned in ../gpio/gpio.txt.
Don't reference legacy docs.
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +additionalProperties:
This style was for existing bindings which had no node name pattern.
Define a pattern for node names.
> + anyOf:
> + - type: object
> + additionalProperties: false
> + allOf:
> + - $ref: pincfg-node.yaml#
> + - $ref: pinmux-node.yaml#
> +
> + description:
> + Pin controller client devices use pin configuration subnodes (children
> + and grandchildren) for desired pin configuration.
> + Client device subnodes use the below standard properties.
> +
> + properties:
> + pinmux:
> + description:
> + Values are constructed from GPIO port number, pin number, and
> + alternate function configuration number using the RZT2H_PORT_PINMUX()
> + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
> + pins: true
> + gpio-hog: true
> + gpios: true
> + input: true
> + input-enable: true
> + output-enable: true
> + output-high: true
> + output-low: true
> + line-name: true
> +
> + - type: object
> + additionalProperties:
> + $ref: "#/additionalProperties/anyOf/0"
Do you really need both 1 OR 2 levels of nodes? Can't you decide on one
way?
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> + - clocks
> + - power-domains
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
> + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> +
> + pinctrl@...c0000 {
> + compatible = "renesas,r9a09g077-pinctrl";
> + reg = <0x802c0000 0x2000>,
> + <0x812c0000 0x2000>,
> + <0x802b0000 0x2000>;
> + reg-names = "nsr", "srs", "srn";
> + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 0 288>;
> + power-domains = <&cpg>;
> +
> + sci_pins: serial0 {
> + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
> + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
> + };
> +
> + sd1-pwr-en-hog {
> + gpio-hog;
> + gpios = <RZT2H_GPIO(39, 2) 0>;
> + output-high;
> + line-name = "sd1_pwr_en";
> + };
> + };
> diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
> new file mode 100644
> index 000000000000..c73a7f25ef5c
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/T2H family pinctrl bindings.
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
> +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
> +
> +#define RZT2H_PINS_PER_PORT 8
> +
> +/*
> + * Create the pin index from its bank and position numbers and store in
> + * the upper 16 bits the alternate function identifier
> + */
> +#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
> +
> +/* Convert a port and pin label to its global pin index */
> +#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin))
> +
> +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
> --
> 2.49.0
>
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