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Message-ID: <175106708298.79260.10445943203117657356.b4-ty@gmail.com>
Date: Sat, 28 Jun 2025 07:31:50 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen Wang <unicorn_wang@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Alexander Sverdlin <alexander.sverdlin@...il.com>,
Yixun Lan <dlan@...too.org>,
Ze Huang <huangze@...t.edu.cn>,
Thomas Bonnefille <thomas.bonnefille@...tlin.com>,
Inochi Amaoto <inochiama@...il.com>
Cc: devicetree@...r.kernel.org,
sophgo@...ts.linux.dev,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Longbin Li <looong.bin@...il.com>
Subject: Re: (subset) [PATCH v4 0/4] riscv: sophgo: cv18xx: Add reset generator support
On Tue, 17 Jun 2025 15:01:38 +0800, Inochi Amaoto wrote:
> Like SG2042, CV1800 Series SoCs also have simple bit reset generator.
> Add necessary code and bindings for it.
>
> Changes from v4:
> 1. patch 1: convert the compatible as entry of enum.
> 1. patch 2, 3: apply Alexander's tag.
> 1. patch 3: apply Junhui's tag.
>
> [...]
Applied to for-next, thanks!
[3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
https://github.com/sophgo/linux/commit/fcb3f47c81afe43b336bf8033234417445789807
[4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
https://github.com/sophgo/linux/commit/880f18ee6772d4add69519cb7de2fcf9f4769cd6
Thanks,
Inochi
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