linux-kernel - Re: SMMUv3 interrupt handling via custom logic

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <43acfcd8-b359-448f-bbb6-da1b71a64f45@arm.com>
Date: Fri, 27 Jun 2025 11:42:48 +0100
From: Robin Murphy <robin.murphy@....com>
To: Michal Simek <michal.simek@....com>, Will Deacon <will@...nel.org>,
 "Stabellini, Stefano" <stefano.stabellini@....com>
Cc: linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
 iommu@...ts.linux.dev,
 Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
 "Sarangi, Anirudha" <anirudha.sarangi@....com>
Subject: Re: SMMUv3 interrupt handling via custom logic

On 2025-06-27 8:19 am, Michal Simek wrote:
> Hi Will and Robin, (+Stefano, Anirudha)
> 
> We are using smmu-v3 in our SOC and I would like to ask you for 
> recommendation how to handle our interrupt cases.
> 
> here is description which we are using
> 
> smmu: iommu@...00000 {
>      compatible = "arm,smmu-v3";
>      reg = <...>;
>      #iommu-cells = <1>;
>      interrupt-names = "combined";
>      interrupts = <0 169 4>;
> };
> 
> but it is missing one important detail which just arise that actually 
> there is additional HW logic which deals with SMMU interrupts separately.
> There is a secure part (global, cmd, event - gerror, cmdq-sync, eventq 
> in DT)
> and non secure part (pri, global, cmd, event - priq, gerror, cmdq-sync, 
> eventq in DT).
> Based on my information all these interrupts should be acked once 
> handled to be able to get another one.
> The driver itself is able to handle them separately but we didn't create 
> any solution to reach custom HW to do it.
> 
> I looked at f935448acf46 ("iommu/arm-smmu-v3: Add workaround for Cavium 
> ThunderX2 erratum #126") which introduced combined IRQs but it looks 
> like that there is no need for additional ACK of that IRQs.

Per the architecture, SMMU interrupts are logically edge-triggered so 
there is nothing to clear at the SMMU end (the "interrupt status" is 
implicit in whatever condition caused an interrupt to be sent, e.g. the 
event queue becoming non-empty, SMMU_GERROR becoming different from 
SMMU_GERRORN, etc.)

If this is an Arm SMMU IP (MMU-600/700/S3) then the physical interrupt 
outputs are most definitely rising-edge. If somone's stuck some 
interrupt combiner in between those and the main interrupt controller, 
then yes, that interrupt combiner really should have its own driver.

> The HW logic itself is handling secure and non secure settings for SMMU 
> that's why would be the best to avoid directly mapping it in Linux.
> 
> One way to go is to create secondary interrupt controller driver
> a) ioremap one with notice about secure part because we are using SMMU 
> only with NS world
> b) firmware based to tunnel accesses via SMCs and allow only access to 
> limited amount of registers
> 
> The second way is likely create any hooks in the driver to be able to 
> provide additional SOC specific hooks.

If this thing is munging *all* the SMMU interrupt outputs as I suspect, 
then the big problem with that idea is that "the driver" is at least two 
separate drivers (SMMU and PMU), 3 if it has RAS and you ever want to 
entertain the idea of kernel-first handling.

Thanks,
Robin.

> 
> I am not quite sure which way would be the best that's why I would like 
> to get some recommendation from you.
> 
> Stefano: please correct me if any of my description is not accurate.
> 
> Thanks,
> Michal