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Message-ID: <667ac51f-d19d-4832-9aa6-97d9a86e0068@oss.qualcomm.com>
Date: Fri, 27 Jun 2025 15:37:09 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Taniya Das <quic_tdas@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v10 01/10] clk: qcom: clk-alpha-pll: Add support for
dynamic update for slewing PLLs
On 27/06/2025 13:13, Taniya Das wrote:
>
>
> On 6/25/2025 5:17 PM, Dmitry Baryshkov wrote:
>> On Wed, Jun 25, 2025 at 04:13:26PM +0530, Taniya Das wrote:
>>> The alpha PLLs which slew to a new frequency at runtime would require
>>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
>>> which can support the slewing of the PLL to a new frequency.
>>>
>>> Reviewed-by: Imran Shaik <quic_imrashai@...cinc.com>
>>> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
>>> ---
>>> drivers/clk/qcom/clk-alpha-pll.c | 169 +++++++++++++++++++++++++++++++++++++++
>>> drivers/clk/qcom/clk-alpha-pll.h | 1 +
>>> 2 files changed, 170 insertions(+)
>>>
>
>>> + /*
>>> + * Dynamic pll update will not support switching frequencies across
>>> + * vco ranges. In those cases fall back to normal alpha set rate.
>>> + */
>>> + if (curr_vco->val != vco->val)
>>> + return clk_alpha_pll_set_rate(hw, rate, parent_rate);
>>> +
>>> + a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
>>> +
>>> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
>>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a));
>>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a));
>>
>> We have code that does this in __clk_alpha_pll_set_rate() and now you
>> are adding two more copies. Please extract PLL_L_VAL, PLL_ALPHA_VAL and
>> PLL_USER_CTL / PLL_VCO_MASK into a helper function.
>>
>
> Dmitry, I was thinking of implementing the following as a reusable
> helper since it can be leveraged by most of the functions. I'd
> appreciate your suggestions or feedback.
The code below looks good to me. Please use 'alpha' instead of 'a'.
>
> static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll,
> const struct pll_vco *vco, u32 l, u64 a, u32 alpha_width, bool alpha_en)
> {
> regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
>
> if (alpha_width > ALPHA_BITWIDTH)
> a <<= alpha_width - ALPHA_BITWIDTH;
>
> if (alpha_width > 32)
> regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a));
>
> regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a));
>
> if (vco) {
> regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
> PLL_VCO_MASK << PLL_VCO_SHIFT,
> vco->val << PLL_VCO_SHIFT);
> }
>
> if (alpha_en)
> regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN);
> }
>
>
>>> +
>>> + /* Ensure that the write above goes before slewing the PLL */
>>> + mb();
>>> +
>>> + if (clk_hw_is_enabled(hw))
>>> + return clk_alpha_pll_slew_update(pll);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +/*
>>> + * Slewing plls should be bought up at frequency which is in the middle of the
>>> + * desired VCO range. So after bringing up the pll at calibration freq, set it
>>> + * back to desired frequency(that was set by previous clk_set_rate).
>
>>>
>>
>
--
With best wishes
Dmitry
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