linux-kernel - RE: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

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Message-ID:
 <OSCPR01MB14647BA02F34A7BA3C98D6CCFFF46A@OSCPR01MB14647.jpnprd01.prod.outlook.com>
Date: Mon, 30 Jun 2025 16:53:50 +0000
From: John Madieu <john.madieu.xa@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: "magnus.damm@...il.com" <magnus.damm@...il.com>, "robh@...nel.org"
	<robh@...nel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>, "mturquette@...libre.com"
	<mturquette@...libre.com>, "sboyd@...nel.org" <sboyd@...nel.org>,
	"richardcochran@...il.com" <richardcochran@...il.com>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>, Biju Das
	<biju.das.jz@...renesas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset
 signals for the GBETH IPs

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: Wednesday, June 25, 2025 5:13 PM
> To: John Madieu <john.madieu.xa@...renesas.com>
> Subject: Re: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
> 
> Hi John,
> 
> On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@...renesas.com>
> wrote:
> > Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
> > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > dividers, and mux clocks needed by these two GBETH IPs.
> >
> > Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
> > Tested-by: Biju Das <biju.das.jz@...renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
> > ---
> >
> > v2:
> > No changes but resending without dt-bindings patch
> >
> > v3:
> > Uses underscores instead of dashes in clock names
> 
> Thanks for the update!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> 
> > +
> >  /* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
> > +"et0_rxc_rx_clk" }; static const char * const smux2_gbe0_txclk[] = {
> > +".plleth_gbe0", "et0_txc_tx_clk" }; static const char * const
> > +smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" }; static
> > +const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
> > +"et1_txc_tx_clk" };
> 
> I have to ask you again: these still differ from the similar names used on
> RZ/V2H. Is there a reason for that? Will that cause issues later?
> Or is this to be sorted out only when the PHY driver will start supporting
> these clocks?
> 

I've discussed internally, and names must match. The next version will
then have appropriate names. Sorry for not mentioning it earlier.

> >  static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3",
> > ".pllcm33_div4" };  static const char * const smux2_xspi_clk1[] = {
> > ".smux2_xspi_clk0", ".pllcm33_div5" };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert

Regards,
John

> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds