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Message-ID: <86jz4tb14h.wl-maz@kernel.org>
Date: Mon, 30 Jun 2025 18:17:02 +0100
From: Marc Zyngier <maz@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	Arnd Bergmann <arnd@...db.de>,
	Sascha Bischoff <sascha.bischoff@....com>,
	Jonathan Cameron <Jonathan.Cameron@...wei.com>,
	Timothy Hayes <timothy.hayes@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	"Liam R. Howlett" <Liam.Howlett@...cle.com>,
	Peter Maydell <peter.maydell@...aro.org>,
	Mark Rutland <mark.rutland@....com>,
	Jiri Slaby <jirislaby@...nel.org>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-pci@...r.kernel.org
Subject: Re: [PATCH v6 00/31] Arm GICv5: Host driver implementation

On Thu, 26 Jun 2025 11:25:51 +0100,
Lorenzo Pieralisi <lpieralisi@...nel.org> wrote:
> 
> Implement the irqchip kernel driver for the Arm GICv5 architecture,
> as described in the GICv5 beta0 specification, available at:
> 
> https://developer.arm.com/documentation/aes0070
> 
> The GICv5 architecture is composed of multiple components:
> 
> - one or more IRS (Interrupt Routing Service)
> - zero or more ITS (Interrupt Translation Service)
> - zero or more IWB (Interrupt Wire Bridge)

[...]

I think what is here is pretty solid, and definitely in a better shape
than the equivalent GICv3 support patches at a similar point in the
lifetime of the architecture.

For patches in this series except patch 18:

Reviewed-by: Marc Zyngier <maz@...nel.org>

If this goes into 6.17 (which I hope), it'd be good to have this
series on a stable branch so that we can take the corresponding KVM
patches[1] independently if they are deemed in a good enough state.

	M.

[1] https://lore.kernel.org/r/20250627100847.1022515-1-sascha.bischoff@arm.com

-- 
Without deviation from the norm, progress is not possible.

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