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Message-ID: <3c3c912c-1f33-4f63-9a37-fe4db5d23527@sirena.org.uk>
Date: Tue, 1 Jul 2025 15:36:21 +0100
From: Mark Brown <broonie@...nel.org>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: James Clark <james.clark@...aro.org>,
	Vladimir Oltean <olteanv@...il.com>, Arnd Bergmann <arnd@...db.de>,
	Larisa Grigore <larisa.grigore@....com>,
	Frank Li <Frank.li@....com>, Christoph Hellwig <hch@....de>,
	linux-spi@...r.kernel.org, imx@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 0/6] spi: spi-fsl-dspi: Target mode improvements

On Tue, Jul 01, 2025 at 04:57:47PM +0300, Vladimir Oltean wrote:

> Here, the synchronization offsets in DMA mode are an order of magnitude
> worse, so yeah, initial enthusiasm definitely curbed now.

> For me, what matters is not the latency itself, but the ability to
> cross-timestamp one byte within the SPI transfer with high granularity,
> and for the uncertainty of that timestamp to be as small and constant as
> possible.

This is sounding like a copybreak type situation with the mode selected
depending on how big the transfer is, that's a very common pattern.
I've not looked how easy it is to flip this hardware between modes
though.

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