linux-kernel - Re: [PATCH v4 0/6] spi: spi-fsl-dspi: Target mode improvements

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Message-ID: <20250701145312.zx56ji4vvaoxwzkc@skbuf>
Date: Tue, 1 Jul 2025 17:53:12 +0300
From: Vladimir Oltean <vladimir.oltean@....com>
To: Mark Brown <broonie@...nel.org>
Cc: James Clark <james.clark@...aro.org>,
	Vladimir Oltean <olteanv@...il.com>, Arnd Bergmann <arnd@...db.de>,
	Larisa Grigore <larisa.grigore@....com>,
	Frank Li <Frank.li@....com>, Christoph Hellwig <hch@....de>,
	linux-spi@...r.kernel.org, imx@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 0/6] spi: spi-fsl-dspi: Target mode improvements

On Tue, Jul 01, 2025 at 03:36:21PM +0100, Mark Brown wrote:
> On Tue, Jul 01, 2025 at 04:57:47PM +0300, Vladimir Oltean wrote:
> 
> > Here, the synchronization offsets in DMA mode are an order of magnitude
> > worse, so yeah, initial enthusiasm definitely curbed now.
> 
> > For me, what matters is not the latency itself, but the ability to
> > cross-timestamp one byte within the SPI transfer with high granularity,
> > and for the uncertainty of that timestamp to be as small and constant as
> > possible.
> 
> This is sounding like a copybreak type situation with the mode selected
> depending on how big the transfer is, that's a very common pattern.
> I've not looked how easy it is to flip this hardware between modes
> though.

I suppose one could try using FIFO mode for transfers which request
timestamping and DMA for transfers which don't. I don't have an insight
into what impact that will have on the driver, but I suspect at the very
least one will have to transform "DSPI_DMA_MODE" into "dspi->dma_available"
and "dspi->dma_in_use", and reconfigure the SPI_RSER register (interrupt
routing, to DMA engine or to CPUs) at every transfer rather than at dspi_init().

The question is whether you would be willing to see and maintain such
complexity increase, when AFAIK, the LS1028A FIFO mode passes its
requirements.