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Message-Id: <20250701-arm_cs_pm_fix_v3-v2-19-23ebb864fcc1@arm.com>
Date: Tue, 01 Jul 2025 15:53:44 +0100
From: Leo Yan <leo.yan@....com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>, James Clark <james.clark@...aro.org>,
Levi Yun <yeoreum.yun@....com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Yabin Cui <yabinc@...gle.com>, Keita Morisaki <keyz@...gle.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Leo Yan <leo.yan@....com>
Subject: [PATCH v2 19/28] coresight: cti: Introduce CS_MODE_DEBUG mode
Introduce a new CS_MODE_DEBUG mode to indicate that a device is being
used for debugging purposes, e.g, if a system enables CTI for debugging
but not for hardware trace
Update ETM4x driver to mute compiler warnings for the newly added mode.
Signed-off-by: Leo Yan <leo.yan@....com>
---
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
include/linux/coresight.h | 9 +++++----
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
index 572b80ee96fbf18ec8cf9abc30d109a676dfbc5d..3e0039f75f5aad104cb86561bf37971c7dc4e408 100644
--- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
@@ -112,7 +112,7 @@ static ssize_t enable_store(struct device *dev,
ret = pm_runtime_resume_and_get(dev->parent);
if (ret)
return ret;
- ret = cti_enable(drvdata->csdev, CS_MODE_SYSFS, NULL);
+ ret = cti_enable(drvdata->csdev, CS_MODE_DEBUG, NULL);
if (ret)
pm_runtime_put(dev->parent);
} else {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index d71ac055c3d0b74053279a86ede7e5592f2b2909..93ae8590ae2459db317f6367b6cffbf658b0e2f2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -932,6 +932,7 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
case CS_MODE_PERF:
ret = etm4_enable_perf(csdev, event, path);
break;
+ case CS_MODE_DEBUG:
default:
ret = -EINVAL;
}
@@ -1130,6 +1131,7 @@ static void etm4_disable(struct coresight_device *csdev,
mode = coresight_get_mode(csdev);
switch (mode) {
+ case CS_MODE_DEBUG:
case CS_MODE_DISABLED:
break;
case CS_MODE_SYSFS:
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 4d5c07b7ddc67991a3871851fe45463f92bd32c8..f52e834640b72534ea83ab223aae7544b195bbaa 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -253,10 +253,10 @@ struct coresight_trace_id_map {
* by @coresight_ops.
* @access: Device i/o access abstraction for this device.
* @dev: The device entity associated to this component.
- * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually
- * an 'enum cs_mode' but stored in an atomic type. Access is always
- * through atomic APIs, ensuring SMP-safe synchronisation between
- * racing from sysFS and Perf mode. A compare-and-exchange
+ * @mode: The device mode, i.e sysFS, Perf, debug or disabled. This is
+ * actually an 'enum cs_mode' but stored in an atomic type. Access
+ * is always through atomic APIs, ensuring SMP-safe synchronisation
+ * between racing from sysFS and Perf mode. A compare-and-exchange
* operation is done to atomically claim one mode or the other.
* @refcnt: keep track of what is in use. Only access this outside of the
* device's spinlock when the coresight_mutex held and mode ==
@@ -344,6 +344,7 @@ enum cs_mode {
CS_MODE_DISABLED,
CS_MODE_SYSFS,
CS_MODE_PERF,
+ CS_MODE_DEBUG,
};
#define coresight_ops(csdev) csdev->ops
--
2.34.1
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