linux-kernel - Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw CFMWS, LMH, ED

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Message-ID: <c32cede0-643c-47bb-bfde-93adbcf16155@intel.com>
Date: Tue, 1 Jul 2025 08:23:57 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Gregory Price <gourry@...rry.net>,
 "Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>
Cc: linux-cxl@...r.kernel.org, Davidlohr Bueso <dave@...olabs.net>,
 Jonathan Cameron <jonathan.cameron@...wei.com>,
 Alison Schofield <alison.schofield@...el.com>,
 Vishal Verma <vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>,
 Dan Williams <dan.j.williams@...el.com>, Jonathan Corbet <corbet@....net>,
 linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw
 CFMWS, LMH, ED

On 6/23/25 12:19 PM, Gregory Price wrote:
> On Mon, Jun 23, 2025 at 05:29:02PM +0200, Fabio M. De Francesco wrote:
>> Add documentation on how to resolve conflicts between CXL Fixed Memory
>> Windows, Platform Memory Holes, and Endpoint Decoders.
>>
>> Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@...ux.intel.com>
> 
> I won't block a doc update on a suggestion so
> 
> Reviewed-by: Gregory Price <gourry@...rry.net>
> 
>> +Platform Firmware (BIOS) might reserve part of physical addresses below
>> +4 GB (e.g., the Low Memory Hole that describes PCIe memory space for MMIO
>> +or a requirement for the greater than 8 way interleave CXL regions starting
>> +at address 0). In that case the Window Size value cannot be anymore
>> +constrained to the NIW * 256 MB above-mentioned rule.
> 
> It might be nice to have a diagram that explains this visually, as it's
> difficult for me to understand the implications through words alone...

+1 on request for diagram to explain. We should try to document this issue as clearly as possible. Thank you.

> 
> which is likely why the conflict exists in the first place :]
> 
> ~Gregory