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Message-Id: <20250701-x1e-speedbin-b4-v2-3-a8a7e06d39fb@oss.qualcomm.com>
Date: Tue, 01 Jul 2025 21:50:46 +0530
From: Akhil P Oommen <akhilpo@....qualcomm.com>
To: Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Akhil P Oommen <akhilpo@....qualcomm.com>
Subject: [PATCH v2 3/3] arm64: dts: qcom: x1e80100: Update GPU OPP table
Update the GPU OPP table with new opp levels along with the
speedbin configurations.
Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 57 ++++++++++++++++++++++++++++++++--
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 1 +
2 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 558d7d387d7710770244fcc901f461384dd9b0d4..ae3a84e95bbbb282edcd8e42a860618ca9873b27 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3773,6 +3773,9 @@ gpu: gpu@...0000 {
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
@@ -3785,11 +3788,28 @@ gpu_zap_shader: zap-shader {
gpu_opp_table: opp-table {
compatible = "operating-points-v2-adreno", "operating-points-v2";
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x03>;
+ };
+
+ opp-1375000000 {
+ opp-hz = /bits/ 64 <1375000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x03>;
+ };
+
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
opp-peak-kBps = <16500000>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
};
opp-1175000000 {
@@ -3797,13 +3817,24 @@ opp-1175000000 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
};
- opp-1100000000 {
+ opp-1100000000-0 {
opp-hz = /bits/ 64 <1100000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
+ };
+
+ /* Only applicable for SKUs which has 1100Mhz as Fmax */
+ opp-1100000000-1 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x08>;
};
opp-1000000000 {
@@ -3811,6 +3842,7 @@ opp-1000000000 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82b5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-925000000 {
@@ -3818,6 +3850,7 @@ opp-925000000 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82b5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-800000000 {
@@ -3825,6 +3858,7 @@ opp-800000000 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449219>;
qcom,opp-acd-level = <0xa82c5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-744000000 {
@@ -3832,13 +3866,24 @@ opp-744000000 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <10687500>;
qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x0f>;
};
- opp-687000000 {
+ opp-687000000-0 {
opp-hz = /bits/ 64 <687000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <8171875>;
qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x0f>;
+ };
+
+ /* Only applicable for SKUs which has 687Mhz as Fmax */
+ opp-687000000-1 {
+ opp-hz = /bits/ 64 <687000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x10>;
};
opp-550000000 {
@@ -3846,6 +3891,7 @@ opp-550000000 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074219>;
qcom,opp-acd-level = <0xc0285ffd>;
+ opp-supported-hw = <0x1f>;
};
opp-390000000 {
@@ -3853,6 +3899,7 @@ opp-390000000 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3000000>;
qcom,opp-acd-level = <0xc0285ffd>;
+ opp-supported-hw = <0x1f>;
};
opp-300000000 {
@@ -3860,6 +3907,7 @@ opp-300000000 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136719>;
qcom,opp-acd-level = <0xc02b5ffd>;
+ opp-supported-hw = <0x1f>;
};
};
};
@@ -8250,6 +8298,11 @@ qfprom: efuse@...c8000 {
reg = <0 0x221c8000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ gpu_speed_bin: gpu-speed-bin@119 {
+ reg = <0x119 0x2>;
+ bits = <7 8>;
+ };
};
pmu@...91000 {
diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
index 090659b8bb8942cdcc46f8d4a3e7dbcc043a0f78..c64727e3c00db1e4f8f34da2701061255caa620d 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
@@ -18,6 +18,7 @@
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
+/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
&gcc {
--
2.48.1
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