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Message-Id: <175135578094.10306.3959145621535083465.b4-ty@kernel.org>
Date: Tue, 01 Jul 2025 13:13:00 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: linux-rockchip@...ts.infradead.org,
Geraldo Nascimento <geraldogabriel@...il.com>
Cc: Shawn Lin <shawn.lin@...k-chips.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Rick wertenbroek <rick.wertenbroek@...il.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Valmantas Paliksa <walmis@...il.com>, linux-phy@...ts.infradead.org,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Krzysztof WilczyĆski <kwilczynski@...nel.org>
Subject: Re: (subset) [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver
quality
On Mon, 30 Jun 2025 19:24:15 -0300, Geraldo Nascimento wrote:
> During a 30-day debugging-run fighting quirky PCIe devices on RK3399
> some quality improvements began to take form and after feedback from
> community they reached more polished state.
>
> This will ensure maximum chance of retraining to 5.0GT/s, on all four
> lanes and fix async strobe TEST_WRITE disablement. On top of this,
> standard PCIe defines are now used to reference registers from offset
> at Capabilities Register.
>
> [...]
Applied, thanks!
[1/4] PCI: rockchip: Use standard PCIe defines
commit: a54fa9e656b38d64761478d06aa8679eae074ca1
[2/4] PCI: rockchip: Set Target Link Speed before retraining
commit: 7a886fbf4004a990cb7231d64370c622d0eb741f
Best regards,
--
Manivannan Sadhasivam <mani@...nel.org>
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