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Message-ID: <db1d07f4-f87d-403a-9ab3-bf8e5b9465b3@quicinc.com>
Date: Tue, 1 Jul 2025 20:08:27 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen
 Boyd" <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Georgi Djakov
	<djakov@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Richard Cochran
	<richardcochran@...il.com>,
        Konrad Dybcio <konradybcio@...nel.org>,
        "Catalin
 Marinas" <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Anusha Rao
	<quic_anusha@...cinc.com>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <quic_suruchia@...cinc.com>, <quic_pavir@...cinc.com>
Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock
 controller node



On 6/28/2025 12:27 AM, Konrad Dybcio wrote:
> On 6/27/25 2:09 PM, Luo Jie wrote:
>> NSS clock controller provides the clocks and resets to the networking
>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
>> UNIPHY (PCS) blocks.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 2eea8a078595..eb4aa778269c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -730,6 +730,36 @@ frame@...d000 {
>>   			};
>>   		};
>>   
>> +		clock-controller@...00000 {
>> +			compatible = "qcom,ipq5424-nsscc";
>> +			reg = <0 0x39b00000 0 0x800>;
> 
> size = 0x100_000
> 
> with that:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> Konrad

I initially thought that a block size of 0x800 would be sufficient, as
it covers the maximum address range needed for the clock configurations.
However, the NSS clock controller block actually occupies an address
range of 0x80000. I will update this to 0x80000 in the next version.
Thank you for your feedback.


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