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Message-ID: <CAHCN7x+2A476SgUP3uWSLovpDU0qxxP=a+sXLbdE0UU6Bv+_YQ@mail.gmail.com>
Date: Wed, 2 Jul 2025 09:20:35 -0500
From: Adam Ford <aford173@...il.com>
To: linux-arm-kernel@...ts.infradead.org
Cc: aford@...conembedded.com, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, 
	Pengutronix Kernel Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org, 
	imx@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

On Fri, Jun 20, 2025 at 4:34 PM Adam Ford <aford173@...il.com> wrote:
>
> The reference manual for the i.MX8MM states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
>

Shawn and/or Fabio,

Any chance this can get reviewed and possibly applied for the next kernel?

thank you,

adam

> Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> Signed-off-by: Adam Ford <aford173@...il.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> index 21bcd82fd092..8287a7f66ed3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> @@ -294,6 +294,8 @@ &usdhc3 {
>         pinctrl-0 = <&pinctrl_usdhc3>;
>         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +       assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
> +       assigned-clock-rates = <400000000>;
>         bus-width = <8>;
>         non-removable;
>         status = "okay";
> --
> 2.48.1
>

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