linux-kernel - Re: [PATCH 2/4] arm64: dts: renesas: r9a09g057: Add XSPI node

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Message-ID: <CA+V-a8ucoVPNpeKsXYe+BPSvZVkM96YzQ14_te4O-nBmtY0t0w@mail.gmail.com>
Date: Wed, 2 Jul 2025 21:55:36 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, 
	linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/4] arm64: dts: renesas: r9a09g057: Add XSPI node

Hi Geert,

Thank you for the review.

On Tue, Jul 1, 2025 at 1:08 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add XSPI node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -280,6 +280,29 @@ sys: system-controller@...30000 {
> >                         resets = <&cpg 0x30>;
> >                 };
> >
> > +               xspi: spi@...30000 {
> > +                       compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
> > +                       reg = <0 0x11030000 0 0x10000>,
> > +                             <0 0x20000000 0 0x10000000>;
> > +                       reg-names = "regs", "dirmap";
> > +                       interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > +                       interrupt-names = "pulse", "err_pulse";
> > +                       clocks = <&cpg CPG_MOD 0x9f>,
> > +                                <&cpg CPG_MOD 0xa0>,
> > +                                <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
> > +                                <&cpg CPG_MOD 0xa1>;
> > +                       clock-names = "ahb", "axi", "spi", "spix2";
> > +                       assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
> > +                       assigned-clock-rates = <133333334>;
>
> Same question as [PATCH 1/4].
>
Sure, I'll move this to the board DTS, and also add the comment below
for clarity.

    /*
     * MT25QU512ABB8E12 flash chip is capable of running at 166MHz
     * clock frequency. Set the maximum clock frequency to 133MHz
     * supported by the RZ/V2H SoC.
     */

Cheers,
Prabhakar