linux-kernel - Re: [PATCH v10 12/17] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports

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Message-ID: <1db7c06d-f0a9-4308-878b-f82d6e445311@amd.com>
Date: Wed, 2 Jul 2025 17:07:57 -0500
From: "Bowman, Terry" <terry.bowman@....com>
To: Alison Schofield <alison.schofield@...el.com>,
 Shiju Jose <shiju.jose@...wei.com>
Cc: "dave@...olabs.net" <dave@...olabs.net>,
 Jonathan Cameron <jonathan.cameron@...wei.com>,
 "dave.jiang@...el.com" <dave.jiang@...el.com>,
 "dan.j.williams@...el.com" <dan.j.williams@...el.com>,
 "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
 "ming.li@...omail.com" <ming.li@...omail.com>,
 "Smita.KoralahalliChannabasappa@....com"
 <Smita.KoralahalliChannabasappa@....com>, "rrichter@....com"
 <rrichter@....com>, "dan.carpenter@...aro.org" <dan.carpenter@...aro.org>,
 "PradeepVineshReddy.Kodamati@....com" <PradeepVineshReddy.Kodamati@....com>,
 "lukas@...ner.de" <lukas@...ner.de>,
 "Benjamin.Cheatham@....com" <Benjamin.Cheatham@....com>,
 "sathyanarayanan.kuppuswamy@...ux.intel.com"
 <sathyanarayanan.kuppuswamy@...ux.intel.com>,
 "linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Subject: Re: [PATCH v10 12/17] cxl/pci: Unify CXL trace logging for CXL
 Endpoints and CXL Ports



On 7/1/2025 8:18 PM, Alison Schofield wrote:
> On Fri, Jun 27, 2025 at 12:22:39PM +0000, Shiju Jose wrote:
>>> -----Original Message-----
>>> From: Terry Bowman <terry.bowman@....com>
>>> Sent: 26 June 2025 23:43
>>> To: dave@...olabs.net; Jonathan Cameron <jonathan.cameron@...wei.com>;
>>> dave.jiang@...el.com; alison.schofield@...el.com; dan.j.williams@...el.com;
>>> bhelgaas@...gle.com; Shiju Jose <shiju.jose@...wei.com>;
>>> ming.li@...omail.com; Smita.KoralahalliChannabasappa@....com;
>>> rrichter@....com; dan.carpenter@...aro.org;
>>> PradeepVineshReddy.Kodamati@....com; lukas@...ner.de;
>>> Benjamin.Cheatham@....com;
>>> sathyanarayanan.kuppuswamy@...ux.intel.com; terry.bowman@....com;
>>> linux-cxl@...r.kernel.org
>>> Cc: linux-kernel@...r.kernel.org; linux-pci@...r.kernel.org
>>> Subject: [PATCH v10 12/17] cxl/pci: Unify CXL trace logging for CXL Endpoints
>>> and CXL Ports
>>>
> big snip -
>
>>> -);
>>> -
>>> TRACE_EVENT(cxl_aer_uncorrectable_error,
>>> -	TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32
>>> *hl),
>>> -	TP_ARGS(cxlmd, status, fe, hl),
>>> +	TP_PROTO(struct device *dev, u64 serial, u32 status, u32 fe,
>>> +		 u32 *hl),
>>> +	TP_ARGS(dev, serial, status, fe, hl),
>>> 	TP_STRUCT__entry(
>>> -		__string(memdev, dev_name(&cxlmd->dev))
>>> -		__string(host, dev_name(cxlmd->dev.parent))
>>> +		__string(name, dev_name(dev))
>>> +		__string(parent, dev_name(dev->parent))
>> Hi Terry,
>>
>> Thanks for considering the feedback given in v9 regarding the compatibility issue
>> with the rasdaemon.
>> https://lore.kernel.org/all/959acc682e6e4b52ac0283b37ee21026@huawei.com/
>>
>> Probably some confusion w.r.t the feedback.
>> Unfortunately  TP_printk(...) is not an ABI that we need to keep stable, 
>> it's this structure, TP_STRUCT__entry(..) , that matters to the rasdaemon.
>>
> I'm not so sure you should be letting him off the hook for TP_printk ;)
> It seems TP_printk should be kept aligned w TP_STRUCT_entry(). As a
> user who often looks at TP_printk output, I'd say keep them all in
> sync, and consider them ABI - ie. add to but don't modify.
>
>
I agree. I will keep TP_printk and TP_STRUCT aligned by using 'memdev' and 'host'.
The only change here will be TP_PROTO and will be:
TP_PROTO(struct device *dev, u64 serial, u32 status),

Let me know if that's not ok.

-Terry

>>> 		__field(u64, serial)
>>> 		__field(u32, status)
>>> 		__field(u32, first_error)
>>> 		__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
>>> 	),
>>> 	TP_fast_assign(
>>> -		__assign_str(memdev);
>>> -		__assign_str(host);
>>> -		__entry->serial = cxlmd->cxlds->serial;
>>> +		__assign_str(name);
>>> +		__assign_str(parent);
>>> +		__entry->serial = serial;
>>> 		__entry->status = status;
>>> 		__entry->first_error = fe;
>>> 		/*
>>> @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
>>> 		 */
>>> 		memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
>>> 	),
>>> -	TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error:
>>> '%s'",
>>> -		  __get_str(memdev), __get_str(host), __entry->serial,
>>> +	TP_printk("memdev=%s host=%s serial=%lld status='%s'
>>> first_error='%s'",
>>> +		  __get_str(name), __get_str(parent), __entry->serial,
>>> 		  show_uc_errs(__entry->status),
>>> 		  show_uc_errs(__entry->first_error)
>>> 	)
> snip
>