linux-kernel - [PATCH v4 0/4] Add support for GBETH IPs found on RZ/G3E SoCs

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Message-ID: <20250702005706.1200059-1-john.madieu.xa@bp.renesas.com>
Date: Wed,  2 Jul 2025 02:57:02 +0200
From: John Madieu <john.madieu.xa@...renesas.com>
To: geert+renesas@...der.be,
	magnus.damm@...il.com,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	mturquette@...libre.com,
	sboyd@...nel.org,
	richardcochran@...il.com,
	prabhakar.mahadev-lad.rj@...renesas.com
Cc: linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-clk@...r.kernel.org,
	netdev@...r.kernel.org,
	biju.das.jz@...renesas.com,
	john.madieu@...il.com,
	John Madieu <john.madieu.xa@...renesas.com>
Subject: [PATCH v4 0/4] Add support for GBETH IPs found on RZ/G3E SoCs

Hi all,

This series adds support for the two Gigabit Ethernet (GBETH) interfaces on the
Renesas RZ/G3E (R9A09G047) SoCs and their enablement on the SMARC-II EVK. This
is achieved by integrating the necessary clock/reset signals prior to defining
common DTS nodes, and enabling both GBETH ports at the board level.

Some of the patches from the initial series have already been queued. As the
node enablement required OEN support, this fourth series includes two patches
that add support for OEN on RZ/G3E SoCs.

Changes in v2:
 - Appart from resending the patches and some collected tags, there is no
 changes in V2.
 - Separated binding patch sent as standalone patch can be found here [4]

Changes in v3:
 - Fixed consistency with clock names, replacing dashes with underscores
 - Labeled mdio nodes and used phandle-based override instead of node
 redefinition
 - Minor typo fixes

Changes in v4:
 - Added two patches to add OEN support on G3E for a better description of the hardware
 - Enforced consistency in clock patch to match v2h definitions

OEN pin configuration check logs:

```
root@...rc-rzg3e:/sys/kernel/debug/pinctrl/10410000.pinctrl-pinctrl-rzg2l# cat pinconf-pins | grep PB1  
pin 89 (PB1): input bias disabled, output drive push pull, output enabled, slew rate (0x0), output-impedance (1 x)
root@...rc-rzg3e:/sys/kernel/debug/pinctrl/10410000.pinctrl-pinctrl-rzg2l# cat pinconf-pins | grep PE1
pin 113 (PE1): input bias disabled, output drive push pull, output enabled, slew rate (0x0), output-impedance (1 x)
root@...rc-rzg3e:/sys/kernel/debug/pinctrl/10410000.pinctrl-pinctrl-rzg2l#
```

[1] - https://lore.kernel.org/all/20250604065200.163778-1-john.madieu.xa@bp.renesas.com/
[2] - https://lore.kernel.org/all/20250609083008.0157fe47@kernel.org/
[3] - https://lore.kernel.org/all/20250611061609.15527-1-john.madieu.xa@bp.renesas.com/
[4] - https://lore.kernel.org/all/20250611061204.15393-1-john.madieu.xa@bp.renesas.com/

Regards,
John Madieu

John Madieu (2):
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH)
    interfaces

Lad Prabhakar (2):
  pinctrl: renesas: rzg2l: Pass OEN pin names
  pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC

 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     | 111 ++++++++++++++++++
 drivers/clk/renesas/r9a09g047-cpg.c           |  64 ++++++++++
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       |  63 ++++++++--
 3 files changed, 229 insertions(+), 9 deletions(-)

-- 
2.25.1