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Message-ID: <20250702085927.10370-4-quic_sayalil@quicinc.com>
Date: Wed, 2 Jul 2025 14:29:27 +0530
From: Sayali Lokhande <quic_sayalil@...cinc.com>
To: <andersson@...nel.org>, <konradybcio@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-mmc-owner@...r.kernel.org>
Subject: [PATCH V3 3/3] arm64: dts: qcom: qcs8300-ride: Enable SDHC1 node
Enable sdhc1 support for qcs8300 ride platform.
Signed-off-by: Sayali Lokhande <quic_sayalil@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 8c166ead912c..9c37a0f5ba25 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -17,6 +17,7 @@
aliases {
serial0 = &uart7;
+ mmc0 = &sdhc_1;
};
chosen {
@@ -332,6 +333,26 @@
status = "okay";
};
+&sdhc_1 {
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ vmmc-supply = <&vreg_l8a>;
+ vqmmc-supply = <&vreg_s4a>;
+
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ status = "okay";
+};
+
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
--
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