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Message-ID: <a570b833-0619-4d1a-909f-971ba08f4202@kernel.org>
Date: Wed, 2 Jul 2025 12:30:40 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Albert Yang <yangzh0906@...ndersoft.com>, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, gordon.ge@....ai,
catalin.marinas@....com, geert.uytterhoeven@...il.com, will@...nel.org,
ulf.hansson@...aro.org, adrian.hunter@...el.com, arnd@...db.de
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-mmc@...r.kernel.org, soc@...ts.linux.dev,
bst-upstream@...ai.top, neil.armstrong@...aro.org,
jonathan.cameron@...wei.com, bigfoot@...ssfun.cn, kever.yang@...k-chips.com,
mani@...nel.org, geert+renesas@...der.be, andersson@...nel.org, nm@...com,
nfraprado@...labora.com, quic_tdas@...cinc.com, ebiggers@...gle.com,
victor.shih@...esyslogic.com.tw, shanchun1218@...il.com,
ben.chuang@...esyslogic.com.tw
Subject: Re: [PATCH v2 6/8] arm64: dts: bst: add support for Black Sesame
Technologies C1200 CDCU1.0 board and defconfig
On 02/07/2025 11:44, Albert Yang wrote:
> Add device tree support for the Black Sesame Technologies (BST) C1200
> CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
> family.
>
> The changes include:
> - Adding a new BST device tree directory
> - Adding Makefile entries to build the BST platform device trees
> - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
>
> This board features a quad-core Cortex-A78 CPU, and various peripherals
> including UART, MMC, watchdog timer, and interrupt controller.
>
> ---
> Changes for v2:
> 1. Reorganized memory map into discrete regions
> 2. Updated MMC controller definition:
> - Split into core/CRM register regions
> - Removed deprecated properties
> - Updated compatible string
> 3. Standardized interrupt definitions and numeric formats
> 4. Removed reserved-memory node (superseded by bounce buffers)
> 5. Added root compatible string for platform identification
> 6. Add soc defconfig
>
> Signed-off-by: Ge Gordon <gordon.ge@....ai>
> Signed-off-by: Albert Yang <yangzh0906@...ndersoft.com>
This is messed. SoB does not go to changelog. Apply your patch and look
at result - do you see SoB? No, because changelog is stripped.
submitting patches explains how this is supposed to look like.
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/bst/Makefile | 2 +
> .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 60 +++++++++
> arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++
> arch/arm64/configs/defconfig | 1 +
> 5 files changed, 181 insertions(+)
> create mode 100644 arch/arm64/boot/dts/bst/Makefile
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc2..a39b6cafb644 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -12,6 +12,7 @@ subdir-y += arm
> subdir-y += bitmain
> subdir-y += blaize
> subdir-y += broadcom
> +subdir-y += bst
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
> new file mode 100644
> index 000000000000..4c1b8b4cdad8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
> diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> new file mode 100644
> index 000000000000..4036e0ac2e1d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "bstc1200.dtsi"
> +
> +/ {
> + model = "BST C1200-96 CDCU1.0 4C2G";
> + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@...000000 {
> + device_type = "memory";
> + reg = <0x8 0x10000000 0x0 0x30000000>;
> + };
> +
> + memory@...000000 {
> + device_type = "memory";
> + reg = <0x8 0xc0000000 0x1 0x0>;
> + };
> +
> + memory@...000000 {
> + device_type = "memory";
> + reg = <0xc 0x0 0x0 0x40000000>;
> + };
> +
> + memory@...254000 {
> + device_type = "memory";
> + reg = <0x8 0x254000 0x0 0x1000>;
> + };
> +
> + memory@...151000 {
> + device_type = "memory";
> + reg = <0x8 0x151000 0x0 0x1000>;
> + };
Why do you have multiple memory nodes, not one?
Also, why aren't these sorted according to DTS coding style?
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mmc0_reserved: mmc0@...0000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x5160000 0x0 0x10000>;
> + no-map;
> + };
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + status = "okay";
> + memory-region = <&mmc0_reserved>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> new file mode 100644
> index 000000000000..ddff2cb82cb0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "bst,c1200";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x100>;
Nothing improved. I asked to follow DTS coding style in ordering.
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
You already got this comment. How did you resolve it? You never
responded to comments, so does it mean you just ignored it or something
was not clear? In any case, repeating the same mistake is not getting
this code merged, so respond to comment.
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x200>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x300>;
> + };
> +
> + l2_cache: l2-cache-1 {
l2-cache. Otherwise it is incomplete, so add the second one.
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + clk_mmc: clock-4000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <4000000>;
> + };
> +
> + timer {
t > s
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + always-on;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
Nothing improved. I asked to follow DTS coding style in ordering.
> + interrupt-parent = <&gic>;
> +
> + mmc0: mmc@...00000 {
> + compatible = "bst,c1200-dwcmshc-sdhci";
> + reg = <0x0 0x22200000 0x0 0x1000>,
> + <0x0 0x23006000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_mmc>;
> + clock-names = "core";
> + max-frequency = <200000000>;
> + bus-width = <8>;
> + non-removable;
> + dma-coherent;
> + status = "disabled";
> + };
> +
> + uart0: serial@...08000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-controller;
> + ranges;
> + reg = <0x0 0x32800000 0x0 0x10000>,
> + <0x0 0x32880000 0x0 0x100000>;
Nothing improved. I asked to follow DTS coding style in ordering.
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> + };
> +
> + psci {
p < s, it is really randomly put :/
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +};
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 897fc686e6a9..0a1cfaa19688 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
This is not a DTS patch.
> @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
> CONFIG_ARCH_BRCMSTB=y
> CONFIG_ARCH_BERLIN=y
> CONFIG_ARCH_BLAIZE=y
> +CONFIG_ARCH_BST=y
> CONFIG_ARCH_EXYNOS=y
> CONFIG_ARCH_SPARX5=y
> CONFIG_ARCH_K3=y
Best regards,
Krzysztof
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