linux-kernel - Re: [PATCH v2 5/8] dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC

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Message-ID: <ade0437b-3c23-4174-b4c5-6c90037abf14@quicinc.com>
Date: Wed, 2 Jul 2025 18:33:31 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>, Georgi Djakov <djakov@...nel.org>,
        Philipp Zabel
	<p.zabel@...gutronix.de>,
        Richard Cochran <richardcochran@...il.com>,
        "Konrad
 Dybcio" <konradybcio@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Anusha Rao <quic_anusha@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <quic_suruchia@...cinc.com>, <quic_pavir@...cinc.com>
Subject: Re: [PATCH v2 5/8] dt-bindings: clock: qcom: Add NSS clock controller
 for IPQ5424 SoC



On 7/1/2025 4:22 PM, Krzysztof Kozlowski wrote:
> On Fri, Jun 27, 2025 at 08:09:21PM +0800, Luo Jie wrote:
>> NSS clock controller provides the clocks and resets to the networking
>> blocks such as PPE (Packet Process Engine) and UNIPHY (PCS) on IPQ5424
>> devices.
>>
>> Add the compatible "qcom,ipq5424-nsscc" support based on the current
>> IPQ9574 NSS clock controller DT binding file. ICC clocks are always
>> provided by the NSS clock controller of IPQ9574 and IPQ5424, so add
>> interconnect-cells as required DT property.
>>
>> Also add master/slave ids for IPQ5424 networking interfaces, which is
>> used by nss-ipq5424 driver for providing interconnect services using
>> icc-clk framework.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>>   .../bindings/clock/qcom,ipq9574-nsscc.yaml         | 70 +++++++++++++++++++---
>>   include/dt-bindings/clock/qcom,ipq5424-nsscc.h     | 65 ++++++++++++++++++++
>>   include/dt-bindings/interconnect/qcom,ipq5424.h    | 13 ++++
>>   include/dt-bindings/reset/qcom,ipq5424-nsscc.h     | 46 ++++++++++++++
>>   4 files changed, 186 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
>> index 17252b6ea3be..0029a148a397 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
>> @@ -4,7 +4,7 @@
>>   $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
>>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>>   
>> -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
>> +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
>>   
>>   maintainers:
>>     - Bjorn Andersson <andersson@...nel.org>
>> @@ -12,21 +12,29 @@ maintainers:
>>   
>>   description: |
>>     Qualcomm networking sub system clock control module provides the clocks,
>> -  resets on IPQ9574
>> +  resets on IPQ9574 and IPQ5424
>>   
>> -  See also::
>> +  See also:
>> +    include/dt-bindings/clock/qcom,ipq5424-nsscc.h
>>       include/dt-bindings/clock/qcom,ipq9574-nsscc.h
>> +    include/dt-bindings/reset/qcom,ipq5424-nsscc.h
>>       include/dt-bindings/reset/qcom,ipq9574-nsscc.h
>>   
>>   properties:
>>     compatible:
>> -    const: qcom,ipq9574-nsscc
>> +    enum:
>> +      - qcom,ipq5424-nsscc
>> +      - qcom,ipq9574-nsscc
>>   
>>     clocks:
>>       items:
>>         - description: Board XO source
>> -      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
>> -      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
>> +      - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
>> +          can vary for different IPQ SoCs. For example, it is 1200 MHz on the
>> +          IPQ9574 and 300 MHz on the IPQ5424.
>> +      - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
>> +          rate can vary for different IPQ SoCs. For example, it is 353 MHz
>> +          on the IPQ9574 and 375 MHz on the IPQ5424
>>         - description: GCC GPLL0 OUT AUX clock source
>>         - description: Uniphy0 NSS Rx clock source
>>         - description: Uniphy0 NSS Tx clock source
>> @@ -42,8 +50,12 @@ properties:
>>     clock-names:
>>       items:
>>         - const: xo
>> -      - const: nss_1200
>> -      - const: ppe_353
>> +      - enum:
>> +          - nss_1200
>> +          - nss
> 
> No, that's the same clock.

OK.

> 
> 
>> +      - enum:
>> +          - ppe_353
>> +          - ppe
> 
> No, that's the same clock!
> 
> The frequencies are not part of input pin. Input pin tells you this is
> clock for PPE, not this is clock for PPE 353 and another for PPE xxx.
> 
> Best regards,
> Krzysztof
> 

Ok. Our only concern with dropping the suffix and using a common name
was renaming the existing property (initially added for IPQ9574 SoC)
from 'ppe_353' to 'ppe'. However I do agree that dropping suffix is the
better approach. Thanks for the suggestion.