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Message-ID: <CAK9=C2U7Ze=q12N+_MM5c+nsJEBkuCoHs-GUsM0qdfVSyR2QVQ@mail.gmail.com>
Date: Wed, 2 Jul 2025 16:34:29 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Jonathan Corbet <corbet@....net>, Anup Patel <anup@...infault.org>, 
	Atish Patra <atish.patra@...ux.dev>, Palmer Dabbelt <palmer@...belt.com>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Alexandre Ghiti <alex@...ti.fr>, 
	Andrew Jones <ajones@...tanamicro.com>, linux-doc@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irqchip: riscv-imsic: Add kernel parameter to disable IPIs

On Tue, Jul 1, 2025 at 1:04 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Tue, Jul 01 2025 at 12:00, Anup Patel wrote:
> > On Mon, Jun 30, 2025 at 9:39 PM Thomas Gleixner <tglx@...utronix.de> wrote:
> >> > When injecting IPIs to a set of harts, the IMSIC IPI support will
> >> > do a separate MMIO write to SETIPNUM_LE register of each target
> >> > hart. This means on a platform where IMSIC is trap-n-emulated,
> >> > there will be N MMIO traps when injecting IPI to N target harts
> >> > hence IPIs based on IMSIC software injected MSI is slow compared
> >> > to the SBI IPI extension.
> >> >
> >> > Add a kernel parameter to disable IPIs in IMSIC driver for platforms
> >> > with trap-n-emulated IMSIC.
> >>
> >> Why do you need a kernel parameter for that. If the platform uses trap-n
> >> emulation, then disable the IPI muck automatically, no?
> >>
> > Unfortunately, we don't have DT, ACPI, or any other way of discovering
> > whether underlying IMSIC is trap-n-emulated. In fact, the DT or ACPI
> > passed to a KVM Guest is the same irrespective of whether underlying
> > IMSIC is trap-n-emulated or backed by hardware IMSIC VS-file.
>
> Sigh.
>
> > Using software injected MSIs as IPIs is purely a software choice in the
> > IMSIC driver so this new kernel parameter allows users to override it.
>
> Please add that information to the change log.
>

Okay, I will add these details to the patch description.

Regards,
Anup

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