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Message-ID: <e30e60570f1b4dc99a1c2b42f4c613ac@huawei.com>
Date: Thu, 3 Jul 2025 09:52:39 +0000
From: Shiju Jose <shiju.jose@...wei.com>
To: Li Ming <ming.li@...omail.com>, "akpm@...ux-foundation.org"
<akpm@...ux-foundation.org>, "andriy.shevchenko@...ux.intel.com"
<andriy.shevchenko@...ux.intel.com>, "bhelgaas@...gle.com"
<bhelgaas@...gle.com>, "ilpo.jarvinen@...ux.intel.com"
<ilpo.jarvinen@...ux.intel.com>, "dave@...olabs.net" <dave@...olabs.net>,
Jonathan Cameron <jonathan.cameron@...wei.com>, "dave.jiang@...el.com"
<dave.jiang@...el.com>, "alison.schofield@...el.com"
<alison.schofield@...el.com>, "vishal.l.verma@...el.com"
<vishal.l.verma@...el.com>, "ira.weiny@...el.com" <ira.weiny@...el.com>,
"dan.j.williams@...el.com" <dan.j.williams@...el.com>
CC: "linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation
>-----Original Message-----
>From: Li Ming <ming.li@...omail.com>
>Sent: 02 July 2025 08:20
>To: akpm@...ux-foundation.org; andriy.shevchenko@...ux.intel.com;
>bhelgaas@...gle.com; ilpo.jarvinen@...ux.intel.com; dave@...olabs.net;
>Jonathan Cameron <jonathan.cameron@...wei.com>; dave.jiang@...el.com;
>alison.schofield@...el.com; vishal.l.verma@...el.com; ira.weiny@...el.com;
>dan.j.williams@...el.com; Shiju Jose <shiju.jose@...wei.com>
>Cc: linux-cxl@...r.kernel.org; linux-kernel@...r.kernel.org; Li Ming
><ming.li@...omail.com>
>Subject: [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation
>
>DPA 0 is considered invalid in cxl_do_ppr(), but per Table 8-143. "Get Partition
>Info Output Payload" in CXL r3.2 section 8.2.10.9.2.1 "Get Partition Info(Opcode
>4100h)", it mentions that DPA 0 is a valid address of a CXL device. So the correct
>implementation should be checking if the DPA is in the DPA range of the CXL
>device rather than checking if the DPA is equal to 0.
>
>Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control
>feature")
>Signed-off-by: Li Ming <ming.li@...omail.com>
Hi Ming,
Thanks for the fix.
Just found that, along with Table 8-143, CXL spec 3.2 Device Decode Logic (Page 576) describes as
"The DPA mappings for a device typically start at 'DPA 0' for Decoder[0] and
are sequentially accumulated with each additional decoder used"
Tested-by: Shiju Jose <shiju.jose@...wei.com>
Reviewed-by: Shiju Jose <shiju.jose@...wei.com>
>---
> drivers/cxl/core/edac.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c index
>623aaa4439c4..1cf65b1538b9 100644
>--- a/drivers/cxl/core/edac.c
>+++ b/drivers/cxl/core/edac.c
>@@ -1923,8 +1923,11 @@ static int cxl_ppr_set_nibble_mask(struct device
>*dev, void *drv_data, static int cxl_do_ppr(struct device *dev, void *drv_data,
>u32 val) {
> struct cxl_ppr_context *cxl_ppr_ctx = drv_data;
>+ struct cxl_memdev *cxlmd = cxl_ppr_ctx->cxlmd;
>+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
>
>- if (!cxl_ppr_ctx->dpa || val != EDAC_DO_MEM_REPAIR)
>+ if (!resource_contains_addr(&cxlds->dpa_res, cxl_ppr_ctx->dpa) ||
>+ val != EDAC_DO_MEM_REPAIR)
> return -EINVAL;
>
> return cxl_mem_perform_ppr(cxl_ppr_ctx);
>--
>2.34.1
Thanks,
Shiju
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