linux-kernel - Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes

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Message-ID: <CA+V-a8uW00iMUFfSczBsFsC3JLSK8SbufMhYGd_1XgrZ29C1Cg@mail.gmail.com>
Date: Fri, 4 Jul 2025 18:12:46 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes

Hi Geert,

On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
>
> Hi Geert,
>
> Thank you for the review.
>
> On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > @@ -155,6 +155,46 @@ gic: interrupt-controller@...00000 {
> > >                         interrupt-controller;
> > >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > >                 };
> > > +
> > > +               sdhi0: mmc@...80000  {
> > > +                       compatible = "renesas,sdhi-r9a09g077",
> > > +                                    "renesas,sdhi-r9a09g057";
> > > +                       reg = <0x0 0x92080000 0 0x10000>;
> > > +                       interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                    <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&cpg CPG_MOD 1212>,
> >
> > 1112?
> >
> Agreed (and below).
>
Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register.

Cheers,
Prabhakar