linux-kernel - Re: [PATCH v2 3/3] MIPS: CPS: Optimise delay CPU calibration for SMP

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Message-Id: <0eaf6e01-a690-40de-b858-4e23752486b5@app.fastmail.com>
Date: Fri, 04 Jul 2025 18:46:54 +0100
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Gregory CLEMENT" <gregory.clement@...tlin.com>,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@...ileye.com>,
 Théo Lebrun <theo.lebrun@...tlin.com>,
 "Tawfik Bayouk" <tawfik.bayouk@...ileye.com>,
 "Thomas Petazzoni" <thomas.petazzoni@...tlin.com>,
 "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] MIPS: CPS: Optimise delay CPU calibration for SMP



在2025年7月4日周五 下午4:13，Gregory CLEMENT写道：
> On MIPS architecture with CPS-based SMP support, all CPU cores in the
> same cluster run at the same frequency since they share the same L2
> cache, requiring a fixed CPU/L2 cache ratio.
>
> This allows to implement calibrate_delay_is_known(), which will return
> 0 (triggering calibration) only for the primary CPU of each
> cluster. For other CPUs, we can simply reuse the value from their
> cluster's primary CPU core.
>
> With the introduction of this patch, a configuration running 32 cores
> spread across two clusters sees a significant reduction in boot time
> by approximately 600 milliseconds.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>

Reviewed-by: Jiaxun Yang <jiaxun.yang@...goat.com>

Thanks!

-- 
- Jiaxun