linux-kernel - Re: [PATCH net] net: phy: realtek: Reset after clock enable

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Message-ID: <0310186d-dfc5-406f-8cd1-c393a7c620e8@gmail.com>
Date: Fri, 4 Jul 2025 22:18:29 +0200
From: Heiner Kallweit <hkallweit1@...il.com>
To: Sebastian Reichel <sebastian.reichel@...labora.com>,
 Andrew Lunn <andrew@...n.ch>, Russell King <linux@...linux.org.uk>
Cc: "David S. Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>,
 Florian Fainelli <florian.fainelli@...adcom.com>,
 Detlev Casanova <detlev.casanova@...labora.com>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH net] net: phy: realtek: Reset after clock enable

On 04.07.2025 19:48, Sebastian Reichel wrote:
> On Radxa ROCK 4D boards we are seeing some issues with PHY detection and
> stability (e.g. link loss, or not capable of transceiving packages)
> after new board revisions switched from a dedicated crystal to providing
> the 25 MHz PHY input clock from the SoC instead.
> 
> This board is using a RTL8211F PHY, which is connected to an always-on
> regulator. Unfortunately the datasheet does not explicitly mention the
> power-up sequence regarding the clock, but it seems to assume that the
> clock is always-on (i.e. dedicated crystal).
> 
> By doing an explicit reset after enabling the clock, the issue on the
> boards could no longer be observed.
> 
Is the SoC clock always on after boot? Or may it be disabled e.g.
during system suspend? Then you would have to do the PHY reset also
on resume from suspend.

> Cc: stable@...r.kernel.org
> Fixes: 7300c9b574cc ("net: phy: realtek: Add optional external PHY clock")
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
> ---
>  drivers/net/phy/realtek/realtek_main.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> index c3dcb62574303374666b46a454cd4e10de455d24..3a783f0c3b4f2a4f6aa63a16ad309e3471b0932a 100644
> --- a/drivers/net/phy/realtek/realtek_main.c
> +++ b/drivers/net/phy/realtek/realtek_main.c
> @@ -231,6 +231,10 @@ static int rtl821x_probe(struct phy_device *phydev)
>  		return dev_err_probe(dev, PTR_ERR(priv->clk),
>  				     "failed to get phy clock\n");
>  
> +	/* enabling the clock might produce glitches, so hard-reset the PHY */
> +	phy_device_reset(phydev, 1);
> +	phy_device_reset(phydev, 0);
> +
>  	ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1);
>  	if (ret < 0)
>  		return ret;
> 
> ---
> base-commit: 4c06e63b92038fadb566b652ec3ec04e228931e8
> change-id: 20250704-phy-realtek-clock-fix-6cd393e8cb2a
> 
> Best regards,