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Message-ID: <3551dba1-0c5f-4000-8b95-6a04cd81a027@kernel.org>
Date: Fri, 4 Jul 2025 09:54:27 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jie Gan <quic_jiegan@...cinc.com>, Jie Gan <jie.gan@....qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@....com>, Mike Leach
<mike.leach@...aro.org>, James Clark <james.clark@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/2] Enable CTCU device for QCS8300
On 25/06/2025 02:59, Jie Gan wrote:
>
>
> On 6/24/2025 5:59 PM, Jie Gan wrote:
>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
>> configurations as SA8775p platform.
>
> Hi dear maintainers,
>
> I just realized it would be more efficient to introduce a common
> compatible string for SoCs that include two TMC ETR devices.
>
> Most of these SoCs share the same CTCU data configuration, such as the
"Most" basically disqualifies your idea.
> offsets for the ATID and IRQ registers, because they integrate the same
> version of the CTCU hardware.
>
> So I propose introducing a common compatible string,
> "coresight-ctcu-v2", to simplify the device tree configuration for these
> platforms.
This is explained in writing bindings.
Best regards,
Krzysztof
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