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Message-Id: <20250704094109.3646314-1-hector.palacios@digi.com>
Date: Fri, 4 Jul 2025 11:41:09 +0200
From: Hector Palacios <hector.palacios@...i.com>
To: bbrezillon@...nel.org
Cc: korotkov.maxim.s@...il.com,
miquel.raynal@...tlin.com,
linux-mtd@...ts.infradead.org,
linux-kernel@...r.kernel.org,
hector.palacios@...i.com
Subject: [PATCH] mtd: rawnand: hynix: don't try read-retry on SLC NANDs
Some SLC NANDs like H27U4G8F2D expose a valid JEDEC ID yet they don't
support the read-retry mechanism, and fail.
Since SLC NANDs don't require read-retry, continue only if the bits per
cell is bigger than 1.
Signed-off-by: Hector Palacios <hector.palacios@...i.com>
---
drivers/mtd/nand/raw/nand_hynix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
index c02e50608816..b663659b2f49 100644
--- a/drivers/mtd/nand/raw/nand_hynix.c
+++ b/drivers/mtd/nand/raw/nand_hynix.c
@@ -377,9 +377,9 @@ static int hynix_nand_rr_init(struct nand_chip *chip)
/*
* We only support read-retry for 1xnm NANDs, and those NANDs all
- * expose a valid JEDEC ID.
+ * expose a valid JEDEC ID. SLC NANDs don't require read-retry.
*/
- if (valid_jedecid) {
+ if (valid_jedecid && nanddev_bits_per_cell(&chip->base) > 1) {
u8 nand_tech = chip->id.data[5] >> 4;
/* 1xnm technology */
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