linux-kernel - Re: [PATCH] iommu/amd: Enable PASID and ATS capabilities in the correct order

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Message-ID: <64454198-4406-4933-bbcc-426132aea2ff@amd.com>
Date: Sat, 5 Jul 2025 10:01:40 +0530
From: Vasant Hegde <vasant.hegde@....com>
To: Easwar Hariharan <eahariha@...ux.microsoft.com>,
 Joerg Roedel <joro@...tes.org>,
 Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
 Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
 Jason Gunthorpe <jgg@...pe.ca>, Jerry Snitselaar <jsnitsel@...hat.com>,
 "open list:AMD IOMMU (AMD-VI)" <iommu@...ts.linux.dev>,
 open list <linux-kernel@...r.kernel.org>
Cc: Jason Gunthorpe <jgg@...dia.com>
Subject: Re: [PATCH] iommu/amd: Enable PASID and ATS capabilities in the
 correct order



On 7/3/2025 9:24 PM, Easwar Hariharan wrote:
> Per the PCIe spec, behavior of the PASID capability is undefined if the
> value of the PASID Enable bit changes while the Enable bit of the
> function's ATS control register is Set. Unfortunately,
> pdev_enable_caps() does exactly that by ordering enabling ATS for the
> device before enabling PASID.
> > Cc: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
> Cc: Vasant Hegde <vasant.hegde@....com>
> Cc: Jason Gunthorpe <jgg@...dia.com>
> Cc: Jerry Snitselaar <jsnitsel@...hat.com>
> Fixes: eda8c2860ab679 ("iommu/amd: Enable device ATS/PASID/PRI capabilities independently")
> Signed-off-by: Easwar Hariharan <eahariha@...ux.microsoft.com>

Patch looks good.

Reviewed-by: Vasant Hegde <vasant.hegde@....com>


-Vasant



> ---
>  drivers/iommu/amd/iommu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 3117d99cf83d..8b8d3e843743 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -634,8 +634,8 @@ static inline void pdev_disable_cap_pasid(struct pci_dev *pdev)
>  
>  static void pdev_enable_caps(struct pci_dev *pdev)
>  {
> -	pdev_enable_cap_ats(pdev);
>  	pdev_enable_cap_pasid(pdev);
> +	pdev_enable_cap_ats(pdev);
>  	pdev_enable_cap_pri(pdev);
>  }
>