lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <5453371.fEcJ0Lxnt5@diego> Date: Sun, 06 Jul 2025 12:23:26 +0200 From: Heiko Stübner <heiko@...ech.de> To: linux-kernel@...r.kernel.org, Detlev Casanova <detlev.casanova@...labora.com> Cc: Sandy Huang <hjc@...k-chips.com>, Andy Yan <andy.yan@...k-chips.com>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko.stuebner@...rry.de>, Sebastian Reichel <sebastian.reichel@...labora.com>, Dragan Simic <dsimic@...jaro.org>, Alexey Charkov <alchark@...il.com>, Jianfeng Liu <liujianfeng1994@...il.com>, Cristian Ciocaltea <cristian.ciocaltea@...labora.com>, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, kernel@...labora.com, Detlev Casanova <detlev.casanova@...labora.com>, Conor Dooley <conor.dooley@...rochip.com> Subject: Re: [PATCH v4 1/3] dt-bindings: display: vop2: Add VP clock resets Am Freitag, 15. November 2024, 17:20:40 Mitteleuropäische Sommerzeit schrieb Detlev Casanova: > Add the documentation for VOP2 video ports reset clocks. > One reset can be set per video port. > > Reviewed-by: Conor Dooley <conor.dooley@...rochip.com> > Signed-off-by: Detlev Casanova <detlev.casanova@...labora.com> > --- > .../display/rockchip/rockchip-vop2.yaml | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > index 2531726af306b..5b59d91de47bd 100644 > --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -65,6 +65,26 @@ properties: > - const: dclk_vp3 > - const: pclk_vop > > + resets: > + minItems: 5 > + items: > + - description: AXI clock reset. > + - description: AHB clock reset. > + - description: Pixel clock reset for video port 0. > + - description: Pixel clock reset for video port 1. > + - description: Pixel clock reset for video port 2. > + - description: Pixel clock reset for video port 3. > + > + reset-names: > + minItems: 5 > + items: > + - const: aclk > + - const: hclk the vop1 uses "axi" and "ahb" (and "dclk") for these reset names. The vendor vop2 code also uses that name in comments, like /* * Reset AXI to get a clean state, which is conducive to recovering * from exceptions when enable at next time(such as iommu page fault) */ So for these two we're not resetting clocks, but the parts of the vop2 ... so I'd strongly wish for matching names for the vop2 :-) Thanks Heiko > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + - const: dclk_vp3 > + > rockchip,grf: > $ref: /schemas/types.yaml#/definitions/phandle > description: > @@ -128,6 +148,11 @@ allOf: > clock-names: > minItems: 7 > > + resets: > + minItems: 6 > + reset-names: > + minItems: 6 > + > ports: > required: > - port@0 > @@ -152,6 +177,11 @@ allOf: > clock-names: > maxItems: 5 > > + resets: > + maxItems: 5 > + reset-names: > + maxItems: 5 > + > ports: > required: > - port@0 > @@ -183,6 +213,16 @@ examples: > "dclk_vp0", > "dclk_vp1", > "dclk_vp2"; > + resets = <&cru SRST_A_VOP>, > + <&cru SRST_H_VOP>, > + <&cru SRST_VOP0>, > + <&cru SRST_VOP1>, > + <&cru SRST_VOP2>; > + reset-names = "aclk", > + "hclk", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > power-domains = <&power RK3568_PD_VO>; > iommus = <&vop_mmu>; > vop_out: ports { >
Powered by blists - more mailing lists