linux-kernel - Re: [PATCH net-next v13 00/12] Add Microchip ZL3073x support (part 1)

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Message-ID: <cdvecjk7sz66hnoue32nlhwlbghyqkc7rk4ri2me2oioty6aiv@nf7v2bjj63h5>
Date: Mon, 7 Jul 2025 10:28:07 +0200
From: Jiri Pirko <jiri@...nulli.us>
To: Ivan Vecera <ivecera@...hat.com>
Cc: netdev@...r.kernel.org, Vadim Fedorenko <vadim.fedorenko@...ux.dev>, 
	Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Prathosh Satish <Prathosh.Satish@...rochip.com>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, 
	Paolo Abeni <pabeni@...hat.com>, Simon Horman <horms@...nel.org>, 
	Jonathan Corbet <corbet@....net>, Jason Gunthorpe <jgg@...pe.ca>, 
	Shannon Nelson <shannon.nelson@....com>, Dave Jiang <dave.jiang@...el.com>, 
	Jonathan Cameron <Jonathan.Cameron@...wei.com>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-doc@...r.kernel.org, Michal Schmidt <mschmidt@...hat.com>, 
	Petr Oros <poros@...hat.com>
Subject: Re: [PATCH net-next v13 00/12] Add Microchip ZL3073x support (part 1)

Fri, Jul 04, 2025 at 08:21:50PM +0200, ivecera@...hat.com wrote:
>Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
>provides DPLL and PTP functionality. This series bring first part
>that adds the core functionality and basic DPLL support.
>
>The next part of the series will bring additional DPLL functionality
>like eSync support, phase offset and frequency offset reporting and
>phase adjustments.
>
>Testing was done by myself and by Prathosh Satish on Microchip EDS2
>development board with ZL30732 DPLL chip connected over I2C bus.
>
>---
>Changelog:
>v13:
>* added support for u64 devlink parameters
>* added support for generic devlink parameter 'clock_id'

When do you plan to add the code which gets the clock_id from the
devicetree? I'm asking as I believe that should be the default.
getrandom/param_set is fallback.